Commits · 6090c148dcbade304c96ae62c828c15a58671a9d · Lorenzo Albano / LLVM bpEVL · GitLab

Dec 13, 2017
- [Targets] Don't automatically include the scheduler class enum from... · ac59db2e
  Craig Topper authored Dec 13, 2017
  ac59db2e
- Rename LiveIntervalAnalysis.h to LiveIntervals.h · f842297d
  Matthias Braun authored Dec 13, 2017
  f842297d
Dec 12, 2017
- [Hexagon] Better detection of identity and undef masks in shuffles · edcd9dcb
  Krzysztof Parzyszek authored Dec 12, 2017
  edcd9dcb
- [Hexagon] Fix wrong order of operands for vmux · 40a605f1
  Krzysztof Parzyszek authored Dec 12, 2017
  40a605f1
- Reapply "[X86] Flag BroadWell scheduler model as complete" · 1074eb22
  Sanjoy Das authored Dec 12, 2017
  1074eb22
- Revert "[X86] Flag BroadWell scheduler model as complete" · 81a4a02c
  Sanjoy Das authored Dec 12, 2017
  81a4a02c
- [X86] Add a couple TODOs about missing coverage/features motivated by D40335 · 712a209d
  Craig Topper authored Dec 12, 2017
  712a209d
- [X86] Cleanup type conversion of 64-bit load-store pairs. · 674d053d
  Nirav Dave authored Dec 12, 2017
  674d053d
- [MachineOperand][MIR] Add isRenamable to MachineOperand. · 60c43102
  Geoff Berry authored Dec 12, 2017
  60c43102
- [X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636) · 68f9accf
  Simon Pilgrim authored Dec 12, 2017
  68f9accf
- [RISCV][NFC] Formatting fix in RISCVInstrInfo.td · c01db1ce
  Alex Bradbury authored Dec 12, 2017
  c01db1ce
- [RISCV] Implement assembler pseudo instructions for RV32I and RV64I · 9ed84c8a
  Alex Bradbury authored Dec 12, 2017
  9ed84c8a
- [RISCV] MC layer support for the instructions added in the privileged spec · 8bba6bfe
  Alex Bradbury authored Dec 12, 2017
  8bba6bfe
- [X86] Recognize constant arrays with special values and replace loads from it... · c2eed926
  Ayman Musa authored Dec 12, 2017
  c2eed926
- [PowerPC] Add branch flag on asm parser-only branch instructions · 6479c72f
  Nemanja Ivanovic authored Dec 12, 2017
  6479c72f
- [PowerPC] Follow-up to r318436 to get the missed CSE opportunities · b0783ccc
  Nemanja Ivanovic authored Dec 12, 2017
  b0783ccc
- Revert r320461 - causing ICE in windows buildss · 0f8a5a41
  Simon Pilgrim authored Dec 12, 2017
  0f8a5a41
- [X86] Use regular expressions more aggressively to reduce the number of... · c8e64ab5
  Craig Topper authored Dec 12, 2017
  c8e64ab5
- [X86] Use Ld scheduler classes for instructions with folded loads. · 468a8133
  Craig Topper authored Dec 12, 2017
  468a8133
- [X86] Correct the FMA3 regular expressions in the znver1 scheduler model. · c1e72c01
  Craig Topper authored Dec 12, 2017
  c1e72c01
Dec 11, 2017
- Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion · efef032f
  Richard Trieu authored Dec 11, 2017
  efef032f
- LSR: Check more intrinsic pointer operands · 3e268cc0
  Matt Arsenault authored Dec 11, 2017
  3e268cc0
- [PowerPC] Partially enable the ISEL expansion pass. · 3b49dc54
  Tony Jiang authored Dec 11, 2017
  3b49dc54
- [Hexagon] Add support for Hexagon V65 · a8ab1b75
  Krzysztof Parzyszek authored Dec 11, 2017
  a8ab1b75
- Normalize line endings. NFCI. · 6d89f407
  Simon Pilgrim authored Dec 11, 2017
  6d89f407
- [X86] Add LWP schedule tests · fabe354b
  Simon Pilgrim authored Dec 11, 2017
  fabe354b
- [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma · ac2b0264
  Dmitry Preobrazhensky authored Dec 11, 2017
  ac2b0264
- [Hexagon] Crash in instruction selection for insert_vector_elt for HVX · 15241459
  Krzysztof Parzyszek authored Dec 11, 2017
  15241459
- [PowerPC] Sign-extend negative constant stores · 50d37a11
  Nemanja Ivanovic authored Dec 11, 2017
  50d37a11
- [RISCV] Add custom CC_RISCV calling convention and improved call support · dc31c61b
  Alex Bradbury authored Dec 11, 2017
  dc31c61b
- [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore · bfb00d4c
  Alex Bradbury authored Dec 11, 2017
  bfb00d4c
- [RISCV] Implement prolog and epilog insertion · b014e3de
  Alex Bradbury authored Dec 11, 2017
  b014e3de
- [ARM] Use ADDCARRY / SUBCARRY · 5ea0f250
  Roger Ferrer Ibanez authored Dec 11, 2017
  5ea0f250
- [RISCV] Support lowering FrameIndex · 660bccec
  Alex Bradbury authored Dec 11, 2017
  660bccec
- [mips] Removal of microMIPS64R6 · d6dada17
  Aleksandar Beserminji authored Dec 11, 2017
  d6dada17
- [AVR] Implement some missing code paths · 2124bcf8
  Dylan McKay authored Dec 11, 2017
  2124bcf8
- [AVR] Fix incorrectly-calculated AVRMCExpr evaluations · ab6204b1
  Dylan McKay authored Dec 11, 2017
  ab6204b1
Dec 10, 2017
- [X86] Add VCOMISDZrr, VCOMISSZrr, VUCOMISDZrr, and VUCOMISSZrr to the skylake server sheduler model · c6a4a972
  Craig Topper authored Dec 10, 2017
  c6a4a972
- [X86] Rename some instructions that start with Int_ to have the _Int at the end. · a0be5a06
  Craig Topper authored Dec 10, 2017
  a0be5a06
- [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns · c493d4f5
  Simon Pilgrim authored Dec 10, 2017
  c493d4f5