Commits · 669bb3111ff0b4b300a2218b88ad71f8e58bebb7 · Lorenzo Albano / LLVM bpEVL · GitLab

Jun 30, 2020
- Mips: Don't store MachineFunction in MipsFunctionInfo · 669bb311
  Matt Arsenault authored Jun 18, 2020
  669bb311
- [AArch64] Add getCFInstrCost, treat branches as free for throughput. · 1ccc4992
  Florian Hahn authored Jun 30, 2020
  1ccc4992
- [SVE] Remove calls to VectorType::getNumElements from AArch64 · ab35ba57
  Christopher Tetreault authored Jun 30, 2020
  ab35ba57
- [ARM] Allow the fabs intrinsic to be tail predicated · 3324e3a6
  Samuel Tebbs authored Jun 30, 2020
  3324e3a6
- [ARM] Allow the usub_sat and ssub_sat intrinsics to be tail predicated · 66fa3139
  Samuel Tebbs authored Jun 30, 2020
  66fa3139
- AMDGPU: Use Register · cac655f2
  Matt Arsenault authored Jun 23, 2020
  
  cac655f2
- X86: Use Register · 249933f2
  Matt Arsenault authored Jun 28, 2020
  
  249933f2
- [ARM][MVE] Tail-predication: clean-up of unused code · af459076
  Sjoerd Meijer authored Jun 29, 2020
  af459076
- [ARM] Allow rounding intrinsics to be tail predicated · d9cb811c
  Samuel Tebbs authored Jun 30, 2020
  d9cb811c
- [X86][SSE] LowerVectorAllZero - add support for masked OR-reductions · 82de0189
  Simon Pilgrim authored Jun 30, 2020
  82de0189
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemcpy to Align · c1cd61e0
  Guillaume Chatelet authored Jun 30, 2020
  c1cd61e0
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemmove to Align · 306d7c69
  Guillaume Chatelet authored Jun 30, 2020
  306d7c69
- [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align · 6a6af30d
  Guillaume Chatelet authored Jun 30, 2020
  6a6af30d
- [SystemZ] Add NoMerge MIFlag · 67648695
  Ilya Leoshkevich authored Jun 30, 2020
  67648695
- AMDGPU/GlobalISel: Select icmp intrinsic · d7173826
  Petar Avramovic authored Jun 30, 2020
  d7173826
- [Alignment][NFC] TargetLowering::allowsMemoryAccess · 5f8bdb3e
  Guillaume Chatelet authored Jun 30, 2020
  5f8bdb3e
- [Alignment][NFC] Migrate PPC, X86 and XCore backends to Align · a976ea32
  Guillaume Chatelet authored Jun 30, 2020
  a976ea32
- [MSP430] Declare comparison LibCalls as returning i16 instead of i32 · 19e75717
  Anatoly Trosinenko authored Jun 30, 2020
  19e75717
- [Alignment][NFC] Migrate AArch64, ARM, Hexagon, MSP and NVPTX backends to Align · 4f5133a4
  Guillaume Chatelet authored Jun 30, 2020
  4f5133a4
- [X86] Remove an isel pattern than can never match. Remove bitcasts of loads from a few others. · 767c9c5b
  Craig Topper authored Jun 30, 2020
  
  767c9c5b
- [SystemZ] Improve handling of ZERO_EXTEND_VECTOR_INREG. · ef7aad0d
  Jonas Paulsson authored Mar 26, 2020
  ef7aad0d
- [X86] Prefer AND over PSHUFB for v64i8 when possible · 9b04d69c
  Craig Topper authored Jun 29, 2020
  9b04d69c
Jun 29, 2020
- [PowerPC] Fix FeatureISA3_1 def in PPC.td to imply FeatureISA3_0. · af9cc2d2
  Lei Huang authored Jun 29, 2020
  
  af9cc2d2
- X86: Use MOV32r0 pseudo instead of directly emitting xor · 27905164
  Matt Arsenault authored Jun 28, 2020
  27905164
- [SVE] Remove calls to VectorType::getNumElements from X86 · 0da1e7eb
  Christopher Tetreault authored Jun 29, 2020
  0da1e7eb
- [PowerPC] Fix crash for shuffle canonicalization with elt 0 from RHS · d2533d96
  Nemanja Ivanovic authored Jun 29, 2020
  d2533d96
- [sve][acle] Implement some of the C intrinsics for brain float. · 67e4330f
  Francesco Petrogalli authored Jun 19, 2020
  67e4330f
- [AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips. · 226cda58
  Christudasan Devadasan authored Jun 17, 2020
  226cda58
- [ARM] Better reductions · deb72ce2
  David Green authored Jun 29, 2020
  deb72ce2
- [X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions (REAPPLIED) · 333aa690
  Simon Pilgrim authored Jun 29, 2020
  333aa690
- [PowerPC] Don't combine SCALAR_TO_VECTOR without VSX · 57ad8f47
  Nemanja Ivanovic authored Jun 29, 2020
  57ad8f47
- AMDGPU: Use IsSSA property check instead of asserting on isSSA · d0b0b252
  Matt Arsenault authored Jun 28, 2020
  d0b0b252
- [RISCV] Split the pseudo instruction splitting pass · 2cb0644f
  Luís Marques authored Jun 29, 2020
  2cb0644f
- [AArch64][SVE] NFCI: Choose consistent naming for predicated SDAG nodes · 39f6a36a
  Sander de Smalen authored Jun 29, 2020
  39f6a36a
- [Alignment][NFC] Migrate AMDGPU backend to Align · 52911428
  Guillaume Chatelet authored Jun 29, 2020
  52911428
- [Alignment][NFC] migrate DataLayout::getPreferredAlignment · 368a5e3a
  Guillaume Chatelet authored Jun 29, 2020
  368a5e3a
- [X86] Add vector support to targetShrinkDemandedConstant for OR/XOR opcodes · 3521ecf1
  Simon Pilgrim authored Jun 29, 2020
  3521ecf1
- [AArch64][SVE] Add bfloat16 support to svext intrinsic · d5fc592b
  Cullen Rhodes authored Jun 19, 2020
  d5fc592b
- [AArch64][SVE] Bail out of performPostLD1Combine for scalable types · bb6603f0
  Kerry McLaughlin authored Jun 29, 2020
  bb6603f0
- [TargetLowering] Add DemandedElts arg to ShrinkDemandedConstant · 973685fc
  Simon Pilgrim authored Jun 29, 2020
  973685fc