llvm-svn: 320628

llvm-svn: 320627

llvm-svn: 320626

llvm-svn: 320625

llvm-svn: 320624

llvm-svn: 320623

llvm-svn: 320622

llvm-svn: 320621

llvm-svn: 320620

llvm-svn: 320619

llvm-svn: 320618

llvm-svn: 320617

When cross-compiling using clang-cl 5.0 (which is currently the latest
stable release of the compiler), the default MS compatibility level is
set to VS 2013, which is too low to build LLVM. Explicitly set the
compatibility level to VS 2017 to support cross-compiling LLVM for
Windows using clang-cl 5.0. This will be a no-op when using clang-cl 6.0
and above, where the default MS compatibility level is already VS 2017.

Differential Revision: https://reviews.llvm.org/D41157

llvm-svn: 320616

CMAKE_CL_64 will never be set when cross-compiling with clang-cl, since
CMake relies on an actual VS environment in order to determine it.
Instead, use the size of a void pointer to determine the bit width of
the host compiler (and therefore the host triple), which works for both
native and cross compilation.

Note that, with the impending advent of Windows on AArch64, assuming
that a 64-bit host == x86_64 isn't correct either, but that's something
to be addressed in a follow-up.

Differential Revision: https://reviews.llvm.org/D41155

llvm-svn: 320615

Stores failed to decode at all since they didn't have a
DecoderNamespace set. Loads worked, but did not change
the register width displayed to match the numbmer of
enabled channels.

The number of printed registers for vaddr is still wrong,
but I don't think that's encoded in the instruction so
there's not much we can do about that.

Image atomics are still broken. MIMG is the same
encoding for SI/VI, but the image atomic classes
are split up into encoding specific versions unlike
every other MIMG instruction. They have isAsmParserOnly
set on them for some reason. dmask is also special for
these, so we probably should not have it as an explicit
operand as it is now.

llvm-svn: 320614

Summary:
See D37528 for a previous (non-deferred) version of this
patch and its description.

Preserves dominance in a deferred manner using a new class
DeferredDominance. This reduces the performance impact of
updating the DominatorTree at every edge insertion and
deletion. A user may call DDT->flush() within JumpThreading
for an up-to-date DT. This patch currently has one flush()
at the end of runImpl() to ensure DT is preserved across
the pass.

LVI is also preserved to help subsequent passes such as
CorrelatedValuePropagation. LVI is simpler to maintain and
is done immediately (not deferred). The code to perfom the
preversation was minimally altered and was simply marked
as preserved for the PassManager to be informed.

This extends the analysis available to JumpThreading for
future enhancements. One example is loop boundary threading.

Reviewers: dberlin, kuhar, sebpop

Reviewed By: kuhar, sebpop

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D40146

llvm-svn: 320612

w.r.t. the paper
"A Practical Improvement to the Partial Redundancy Elimination in SSA Form"
(https://sites.google.com/site/jongsoopark/home/ssapre.pdf)

Proper dominance check was missing here, so having a loopinfo should not be required.
Committing this diff as this fixes the bug, if there are
further concerns, I'll be happy to work on them.

Differential Revision: https://reviews.llvm.org/D39781

llvm-svn: 320607

Shrink wrapping should ignore DBG_VALUEs referring to frame indices,
since the presence of debug information must not affect code
generation.

Differential Revision: https://reviews.llvm.org/D41187

llvm-svn: 320606

The invocation without -no-output would try to lipo the different debug
objects together. This wouldn't work on platforms that don't provide
that utility.

llvm-svn: 320605

llvm-svn: 320603

llvm-svn: 320602

Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.

This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.

Differential revision: https://reviews.llvm.org/D41180

llvm-svn: 320601

llvm-svn: 320600

llvm-svn: 320598

llvm-svn: 320595

llvm-svn: 320589

llvm-svn: 320588

llvm-svn: 320587

llvm-svn: 320586

llvm-svn: 320585

The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431

llvm-svn: 320584

llvm-svn: 320583

llvm-svn: 320582

Add missing RDTSCP itinerary

llvm-svn: 320581

llvm-svn: 320580

Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

llvm-svn: 320575

Differential Revision: https://reviews.llvm.org/D41109

llvm-svn: 320573

Differential Revision: https://reviews.llvm.org/D41110

llvm-svn: 320572

Differential Revision: https://reviews.llvm.org/D41112

llvm-svn: 320571

Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK

We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...

Differential Revision: https://reviews.llvm.org/D41119

llvm-svn: 320570