llvm-svn: 320589

llvm-svn: 320588

llvm-svn: 320587

llvm-svn: 320586

llvm-svn: 320585

The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).

Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.

Differential Revision: https://reviews.llvm.org/D30431

llvm-svn: 320584

llvm-svn: 320583

llvm-svn: 320582

Add missing RDTSCP itinerary

llvm-svn: 320581

llvm-svn: 320580

llvm-svn: 320579

llvm-svn: 320578

llvm-svn: 320577

Reviewers: sammccall, ioeric, hokein

Reviewed By: sammccall

Subscribers: klimek, cfe-commits

Differential Revision: https://reviews.llvm.org/D40486

llvm-svn: 320576

Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.

llvm-svn: 320575

otherwise we will copy an object.

llvm-svn: 320574

Differential Revision: https://reviews.llvm.org/D41109

llvm-svn: 320573

Differential Revision: https://reviews.llvm.org/D41110

llvm-svn: 320572

Differential Revision: https://reviews.llvm.org/D41112

llvm-svn: 320571

Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK

We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...

Differential Revision: https://reviews.llvm.org/D41119

llvm-svn: 320570

Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.

This patch builds upon D40902.

Differential Revision: https://reviews.llvm.org/D41071

Patch by Mario Werner.

llvm-svn: 320569

OpenGL issues should be fixed by now.

llvm-svn: 320568

Add missing case that was not implemented yet.

Differential Revision: https://reviews.llvm.org/D38942

llvm-svn: 320567

Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.

Only debug syntax is affected.

llvm-svn: 320566

[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output

Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.

Only debug syntax is affected.

llvm-svn: 320565

Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.

Only debug syntax is affected.

Differential Revision: https://reviews.llvm.org/D41116

llvm-svn: 320564

Summary: ... in qualified code completion and decl lookup.

Reviewers: ilya-biryukov, arphaman

Reviewed By: ilya-biryukov

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D40562

llvm-svn: 320563

Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.

Differential revision: https://reviews.llvm.org/D40959

llvm-svn: 320562

Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.

To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.

The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).

The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.

Reviewers: zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41065

llvm-svn: 320561

When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.

llvm-svn: 320560

We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.

llvm-svn: 320559

Differential Revision: https://reviews.llvm.org/D40003

Patch by Shiva Chen.

llvm-svn: 320558

NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952

Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106

Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9
llvm-svn: 320557

r320413 triggered cmake configure failures when building with 
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set 
(e.g. to RISCV). This is because that patch moved to passing through 
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD 
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be 
passed through to avoid errors like below:

-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
  The target `RISCV' does not exist.

      It should be one of


  AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore


-- Configuring incomplete, errors occurred!

See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171211/509225.html 
for discussion of this fix.

llvm-svn: 320556

Summary:
 - when the diagnostic has an explicit range, we prefer that
 - if the diagnostic has a fixit, its RemoveRange is our next choice
 - otherwise we try to expand the diagnostic location into a whole token.
   (inspired by VSCode, which does this client-side when given an empty range)
 - if all else fails, we return the zero-width range as now.
   (clients react in different ways to this, highlighting a token or a char)
 - this includes the off-by-one fix from D40860, and borrows heavily from it

Reviewers: rwols, hokein

Subscribers: klimek, ilya-biryukov, cfe-commits

Differential Revision: https://reviews.llvm.org/D41118

llvm-svn: 320555

llvm-svn: 320554

Causes: Assertion `ScaledReg == nullptr' failed.

This actually a revert of rL320551.

llvm-svn: 320553

[Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.

Most of the targets don't need the scheduler class enum.

I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.

llvm-svn: 320552

Enable select instruction handling in complex addr modes.

Reviewers: john.brawn, reames, aaboud
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40634

llvm-svn: 320551

This change makes XRay print the log file output only when the verbosity
level is higher than 0. It reduces the log spam in the default case when
we want XRay running silently, except when there are actual
fatal/serious errors.

We also update the documentation to show how to get the information
after the change to the default behaviour.

llvm-svn: 320550