Commits · 956c90d347be82a93b16c685c25d016018ed99bf · Lorenzo Albano / LLVM bpEVL · GitLab

Feb 23, 2021
- [AMDGPU][SelectionDAG] Don't combine uniform multiplies to MUL_[UI]24 · 52bc2e75
  Nicolai Hähnle authored Aug 03, 2020
  52bc2e75
- [ARM] do not consider sp as deprecated for ldm/stm · e1c3bf6a
  Sjoerd Meijer authored Feb 23, 2021
  e1c3bf6a
- [TTI] Change getOperandsScalarizationOverhead to take Type args · dd2dbf7e
  David Green authored Feb 23, 2021
  dd2dbf7e
- [CostModel] Remove VF from IntrinsicCostAttributes · bd4b61ef
  David Green authored Feb 23, 2021
  bd4b61ef
- [RISCV] vle1.v/vse1.v should be unmasked instructions. · 53c4c2b9
  Hsiangkai Wang authored Feb 23, 2021
  53c4c2b9
- Revert "[WebAssembly] call_indirect issues table number relocs" · 7dc98adb
  Andy Wingo authored Feb 23, 2021
  7dc98adb
- [RISCV] Support insertion of misaligned subvectors · dd68f3cf
  Fraser Cormack authored Feb 18, 2021
  dd68f3cf
- [X86] Support amx-int8 intrinsic. · f8b9035a
  Liu, Chen3 authored Feb 23, 2021
  f8b9035a
- [llvm] Use llvm::drop_begin (NFC) · 4ed47858
  Kazu Hirata authored Feb 22, 2021
  
  4ed47858
- Revert "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt" · 662402a8
  Jessica Paquette authored Feb 22, 2021
  662402a8
- [AArch64][GlobalISel] Make overflow legalization use clampScalar · 8b10aa67
  Cassie Jones authored Feb 22, 2021
  8b10aa67
- [X86][AMX] Lower tile copy instruction. · 8f48ddd1
  Luo, Yuanke authored Feb 20, 2021
  8f48ddd1
- [AMDGPU] Move RPT::getLiveRegs() check under EXPENSIVE_CHECKS · bb16efe2
  Stanislav Mekhanoshin authored Feb 22, 2021
  bb16efe2
Feb 22, 2021
- [RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32. · 3231607c
  Craig Topper authored Feb 22, 2021
  3231607c
- [AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt · 867e379c
  Jessica Paquette authored Feb 19, 2021
  867e379c
- [WebAssembly] Remap branch dests after fixCatchUnwindMismatches · f47a654a
  Heejin Ahn authored Feb 21, 2021
  f47a654a
- [WebAssembly] Support WasmEHFuncInfo serialization · 51fb5bf4
  Heejin Ahn authored Feb 20, 2021
  51fb5bf4
- [WebAssembly] Rename methods in WasmEHFuncInfo (NFC) · a08e609d
  Heejin Ahn authored Feb 21, 2021
  a08e609d
- [RISCV] Add isel support for bitcasts between fixed vector types. · 1cd2a5a7
  Craig Topper authored Feb 22, 2021
  1cd2a5a7
- [AArch64][GlobalISel] Emit G_ASSERT_SEXT for SExt parameters in CallLowering · 95d13c01
  Jessica Paquette authored Feb 17, 2021
  95d13c01
- [RISCV] Custom isel the rest of the vector load/store intrinsics. · 1aeb927f
  Craig Topper authored Feb 22, 2021
  1aeb927f
- [AArch64] Adding SHA3 Intrinsics support · 2c25efcb
  Ryan Santhiraraja authored Feb 22, 2021
  2c25efcb
- [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3 · 48135180
  Dmitry Preobrazhensky authored Feb 22, 2021
  48135180
- [ARM] Remove dead lowering code. NFC · 188f15d9
  David Green authored Feb 22, 2021
  188f15d9
- [ARM] Move double vector insert patterns using vins to DAG combine · 21a4faab
  David Green authored Feb 22, 2021
  21a4faab
- [WebAssembly] call_indirect issues table number relocs · 861dbe1a
  Andy Wingo authored Feb 12, 2021
  861dbe1a
- [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr. · 6ff09ce0
  Amara Emerson authored Feb 21, 2021
  6ff09ce0
Feb 21, 2021
- [X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. · b568d3d6
  Simon Pilgrim authored Feb 21, 2021
  
  b568d3d6
- [X86] Replace explicit constant handling in sub(C1, xor(X, C2)) -> add(xor(X,... · 3ab32c94
  Simon Pilgrim authored Feb 21, 2021
  3ab32c94
- [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM. · 1a6c1ac6
  Craig Topper authored Feb 21, 2021
  1a6c1ac6
- [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - remove unnecessary BITCASTs. · bae04a3e
  Simon Pilgrim authored Feb 21, 2021
  bae04a3e
- [X86][AVX] Fold concat(extract_subvector(v0,c0), extract_subvector(v1,c1)) -> vperm2x128 · a6a258f1
  Simon Pilgrim authored Feb 21, 2021
  a6a258f1
- [X86] Fold bitcast(logic(bitcast(X), Y)) --> logic'(X, bitcast(Y)) for int-int bitcasts · 2885d125
  Simon Pilgrim authored Feb 21, 2021
  2885d125
Feb 20, 2021
- [RISCV] Support extraction of misaligned subvectors · 3e1317fd
  Fraser Cormack authored Feb 18, 2021
  3e1317fd
- [RISCV] Improve register allocation around vector masks · 9aa20cae
  Fraser Cormack authored Feb 19, 2021
  9aa20cae
- [DAG] foldSubToUSubSat - fold sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit))) · 761bbed2
  Simon Pilgrim authored Feb 19, 2021
  761bbed2
- Update BPFAdjustOpt.cpp to accept select form of or as well · e4d751c2
  Juneyoung Lee authored Feb 20, 2021
  e4d751c2
- [AArch64][GlobalISel] Add selection support for G_VECREDUCE of <2 x i32> · 067ec53d
  Amara Emerson authored Feb 20, 2021
  067ec53d
- [RISCV] Teach our custom vector load/store intrinsic isel code to propagate... · 71b68fe5
  Craig Topper authored Feb 19, 2021
  71b68fe5
- Different fix for gcc bug · 3bec7ed5
  Jacques Pienaar authored Feb 19, 2021
  3bec7ed5