inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811

llvm-svn: 208810

Summary:
We know that -(zext V) will always be <= zero, simplify signed icmps
that have these.

Uncovered using http://www.cs.utah.edu/~regehr/souper/

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3754

llvm-svn: 208809

No functionality change.

llvm-svn: 208808

llvm-svn: 208807

llvm-svn: 208805

llvm-svn: 208804

llvm-svn: 208803

Reviewed at http://reviews.llvm.org/D3767

llvm-svn: 208802

llvm-svn: 208800

elaborated-type-specifier, place it in the correct
context.

llvm-svn: 208799

This is just unneccessary - we only create abstract definitions when
we're inlining anyway, so there's no reason to delay this to see if
we're going to inline anything.

llvm-svn: 208798

In r205566, I made a change to Resolver so that Resolver revisit
only archive files in --start-group and --end-group pair. That's
not correct, as it also has to revisit DSO files.

This patch is to fix the issue.

Added a test to demonstrate the fix. I confirmed that it succeeded
before r205566, failed after r205566, and is ok with this patch.

Differential Revision: http://reviews.llvm.org/D3734

llvm-svn: 208797

Fixed SectionLoadHistory::GetSectionLoadListForStopID() to always return a valid "SectionLoadList *". 

<rdar://problem/15818525>

llvm-svn: 208796

llvm-svn: 208795

Missing header for Linux, replaces with iostreams.

llvm-svn: 208794

Reviewed at http://reviews.llvm.org/D3766

llvm-svn: 208793

Reviewed at http://reviews.llvm.org/D3741

llvm-svn: 208792

If the function has the landingpad instruction, then the
handlerdata should be emitted even if the function has
nouwnind attribute.  Otherwise, following code will not
work:

    void test1() noexcept {
      try {
        throw_exception();
      } catch (...) {
        log_unexpected_exception();
      }
    }

Since the cantunwind was incorrectly emitted and the
LSDA is not available.

llvm-svn: 208791

The commit r208166 will cause some regression on ARM EHABI.
This fix has been committed in r208715, and an assertion failure
test case has been committed in r208770.

This commit further extends the unittest so that the actual
value in the handlerdata will be checked.

llvm-svn: 208790

SIZE_T_MAX is not available on Linux.

llvm-svn: 208789

X86: If we have an instruction that sets a flag and a zero test on the input of that instruction try to eliminate the test.

For example
	tzcntl	%edi, %ebx
	testl %edi, %edi
	je	.label

can be rewritten into
	tzcntl	%edi, %ebx
	jb 	.label

A minor complication is that tzcnt sets CF instead of ZF when the input
is zero, we have to rewrite users of the flags from ZF to CF. Currently
we recognize patterns using lzcnt, tzcnt and popcnt.

Differential Revision: http://reviews.llvm.org/D3454

llvm-svn: 208788

None of our tests use /fallback, so this lets us gradually add RTTI
support without breaking projects using /fallback.

llvm-svn: 208787

This affects both the Itanium and Microsoft C++ ABIs.

This is in anticipation of a change to the Itanium C++ ABI, and should
match GCC's current behavior.  The new text will likely be:

"""
Pass an object of class type by value if every copy constructor and
move constructor is deleted or trivial and at least one of them is not
deleted, and the destructor is trivial.
"""
http://sourcerytools.com/pipermail/cxx-abi-dev/2014-May/002728.html

On x86 Windows, we can mostly use the same logic, where we use inalloca
instead of passing by address.  However, on Win64, there are register
parameters, and we have to do what MSVC does.  MSVC ignores the presence
of non-trivial move constructors and only considers the presence of
non-trivial or deleted copy constructors.  If a non-trivial or deleted
copy ctor is present, it passes the argument indirectly.

This change fixes bugs and makes us more ABI compatible with both GCC
and MSVC.

Fixes PR19668.

Reviewers: rsmith

Differential Revision: http://reviews.llvm.org/D3660

llvm-svn: 208786

[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and -mcpu=mips(5|64) does not accept MIPS64r2

Summary:
To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3697

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3698

llvm-svn: 208785

Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

llvm-svn: 208784

llvm-svn: 208783

Checks that the pid reported by $qProcessInfo matches the pid that was
launched as the attach test subject.

test exe now supports "sleep:{sleep_seconds}" command line argument.

llvm-svn: 208782

Now that TableGen handles aliases, these are unneeded. Hopefully more will be
able to go soon.

llvm-svn: 208781

llvm-svn: 208780

Tag the GPGPU codegen test cases as unsupported if the nvptx target is not
included in the current llvm build.

Contributed-by: Yabin Hu <yabin.hwu@gmail.com>
llvm-svn: 208779

llvm-svn: 208778

llvm-svn: 208777

llvm-svn: 208776

llvm-svn: 208775

llvm-svn: 208774

When no matching record is found, getgrnam_r return 0 but sets result to NULL.
Should fix PR19734.

llvm-svn: 208773

This shall fix spurious false positive race reports between fclose() and fopen64().

llvm-svn: 208772

llvm-svn: 208771

llvm-svn: 208770