The cost model should not assume vector casts get completely scalarized, since
on targets that have vector support, the common case is a partial split up to
the legal vector size. So, when a vector cast  gets split, the resulting casts
end up legal and cheap.

Instead of pessimistically assuming scalarization, base TTI can use the costs
the concrete TTI provides for the split vector, plus a fudge factor to account
for the cost of the split itself. This fudge factor is currently 1 by default,
except on AMDGPU where inserts and extracts are considered free.

Differential Revision: http://reviews.llvm.org/D21251

llvm-svn: 274642

These tests are now modeled after the sections nowait test where threads wait
to be released in the first construct (either for or single) and the last thread
skips the last for/single construct and releases those threads.  If the test
fails, then it hangs because an unnecessary barrier is executed in between the
constructs.

llvm-svn: 274641

llvm-svn: 274640

llvm-svn: 274639

http://reviews.llvm.org/D22029

llvm-svn: 274638

This helps to mitigate the conflict between COFF.h and winnt.h, which is
PR28399.

llvm-svn: 274637

llvm-svn: 274636

Differential revision: http://reviews.llvm.org/D22040

llvm-svn: 274635

Patch by: Wei Wang
Differential Revision: http://reviews.llvm.org/D21950

llvm-svn: 274634

This reverts commit 0af5ee9631c7c167dc40498b415876553e314c95.

llvm-svn: 274633

This reverts commit 256b29322c827a2d94da56468c936596f5509032.

llvm-svn: 274632

llvm-svn: 274631

Differential Revision: http://reviews.llvm.org/D21939

llvm-svn: 274629

This includes nested types in the member list, even if there are no members of that type. Note that structs and classes have themselves as an "implicit struct" as the first member, so we skip implicit ones.

Differential Revision: http://reviews.llvm.org/D21705

llvm-svn: 274628

We currently always vectorize induction variables. However, if an induction
variable is only used for counting loop iterations or computing addresses with
getelementptr instructions, we don't need to do this. Vectorizing these trivial
induction variables can create vector code that is difficult to simplify later
on. This is especially true when the unroll factor is greater than one, and we
create vector arithmetic when computing step vectors. With this patch, we check
if an induction variable is only used for counting iterations or computing
addresses, and if so, scalarize the arithmetic when computing step vectors
instead. This allows for greater simplification.

This patch addresses the suboptimal pointer arithmetic sequence seen in
PR27881.

Reference: https://llvm.org/bugs/show_bug.cgi?id=27881
Differential Revision: http://reviews.llvm.org/D21620

llvm-svn: 274627

The prev commit failed on compilation.
A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure.

llvm-svn: 274626

Summary:
We are seeing infrequent failures to launch the inferior process on android. The failing call
seems to be execve(). This adds more logging to see the actual error reported by the call.

Reviewers: tberghammer

Subscribers: tberghammer, lldb-commits, danalbert

Differential Revision: http://reviews.llvm.org/D22039

llvm-svn: 274624

llvm-svn: 274623

Otherwise when extracting these files on a unix system one
ends up with files named like "repro\bar\foo.o".

llvm-svn: 274622

In AddressSanitizer and ThreadSanitizer, let's explicitly set the language of the expression we're evaluating.

llvm-svn: 274621

This is a follow-up for r273544.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.

This commit also removes two command-line flags that weren't used in any of the
tests: widen-vmovs and swift-partial-update-clearance. The former may be easily
replaced with the mattr mechanism, but the latter may not (as it is a subtarget
property, and not a proper feature).

Differential Revision: http://reviews.llvm.org/D21797

llvm-svn: 274620

We already have interceptors for dispatch_source API (e.g. dispatch_source_set_event_handler), but they currently only handle submission synchronization. We also need to synchronize based on the target queue (serial, concurrent), in other words, we need to use dispatch_callback_wrap. This patch implements that.

Differential Revision: http://reviews.llvm.org/D21999

llvm-svn: 274619

Differential revision: http://reviews.llvm.org/D21984

llvm-svn: 274617

This is a follow-up for r273544 and r273853.

The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods.
This commit also marks them as obsolete.

Differential Revision: http://reviews.llvm.org/D21796

llvm-svn: 274616

llvm-svn: 274615

This is a regular maintenance update to ensure the latest version of isl is
tested.

Interesting Changes:

  - AST nodes and expressions are now printed as YAML

llvm-svn: 274614

The patch removes redundant kmov instructions (not all, we still have a lot of work here) and redundant "and" instructions after "setcc".
I use "AssertZero" marker between X86ISD::SETCC node and "truncate" to eliminate extra "and $1" instruction.
I also changed zext, aext and trunc patterns in the .td file. It allows to remove extra "kmov" instruictions.

This patch fixes https://llvm.org/bugs/show_bug.cgi?id=28173.

Fast ISEL mode is not supported correctly for AVX-512. ICMP/FCMP scalar instruction should return result in k-reg. It will be fixed in one of the next patches. I redirected handling of "cmp" to the DAG builder mode. (The code looks worse in one specific test case, but without this fix the new patch fails).

Differential revision: http://reviews.llvm.org/D21956

llvm-svn: 274613

Summary:
Since "AMDGPU: Fix verifier errors in SILowerControlFlow", the logic that
ensures that a non-void-returning shader falls off the end of the last
basic block was effectively disabled, since SI_RETURN is now used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96731

Reviewers: arsenm, tstellarAMD

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21975

llvm-svn: 274612

Differential revision: http://reviews.llvm.org/D21957

llvm-svn: 274611

Revision r178818 added tests for TBAA but was missing negative tests to ensure
that TBAA markers are not emitted when TBAA is off.

Differential Revision: http://reviews.llvm.org/D21295

llvm-svn: 274610

isl is already the default code generator since we switched from CLooG several
years ago.

llvm-svn: 274609

[X86] Use native IR for immediate values 0-7 of packed fp cmp builtins. This makes them the same as what is done when using the SSE builtins for these same encodings.

llvm-svn: 274608

[X86] Remove GCC builtin names from sse/avx packed fp cmp intrinsics so clang can special handle some of the immediate values.

llvm-svn: 274607

llvm-svn: 274606

llvm-svn: 274605

Summary: This patch is an implementation of sema and parsing for the OpenMP composite pragma 'distribute simd'.

Differential Revision: http://reviews.llvm.org/D22007

llvm-svn: 274604

llvm-svn: 274603

[AVX512] Remove GCC builtins from the vplzcntd/q intrinsics so we can emit native IR using the generic ctlz intrinsic in clang.

llvm-svn: 274602

ArrayRef is a little better than passing around a pointer/length pair.

No functional change is intended.

llvm-svn: 274601

llvm-svn: 274600