Commits · c01efe690f01431d8d8552d7ceff968e03af6fd6 · Lorenzo Albano / LLVM bpEVL · GitLab

Apr 09, 2018
- Fix type mismatch between MachineMemOperand constructor and accessors. NFC · c01efe69
  Daniel Sanders authored Apr 09, 2018
  c01efe69
- [GISel] Refactor MachineIRBuilder to allow transformations while · b1c467db
  Aditya Nandakumar authored Apr 09, 2018
  b1c467db
- Support generic expansion of ordered vector reduction (PR36732) · 23c2182c
  Simon Pilgrim authored Apr 09, 2018
  23c2182c
- [MachineLICM] Re-enable hoisting of constant stores · 935474fe
  Zaara Syeda authored Apr 09, 2018
  935474fe
- [CodeGen/AccelTable] Don't emit zero-CU name indexes · eadfac87
  Pavel Labath authored Apr 09, 2018
  eadfac87
- [CodeGen/AccelTable]: Don't emit accelerator entries for functions with no names · 889bf9fe
  Pavel Labath authored Apr 09, 2018
  889bf9fe
- [DAGCombine] Improve ReduceLoad for SRL · 1f4f4d9a
  Sam Parker authored Apr 09, 2018
  1f4f4d9a
- Remove MachineLoopInfo dependency from AsmPrinter. · 8d052a0d
  Michael Zolotukhin authored Apr 09, 2018
  8d052a0d
Apr 08, 2018
- [TargetSchedule] shrink interface for init(); NFCI · 0d7df36c
  Sanjay Patel authored Apr 08, 2018
  0d7df36c
- DAGCombiner: Combine SDIV with non-splat vector pow2 divisor · 7a53f169
  Zvi Rackover authored Apr 08, 2018
  7a53f169
- [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)) · 0eb86c8e
  Guozhi Wei authored Apr 07, 2018
  0eb86c8e
Apr 07, 2018
- [DAGCombiner] Add a combine to turn a build vector of zero extends of extract... · 5b95eae1
  Craig Topper authored Apr 07, 2018
  5b95eae1
- Reapply ARM: Do not spill CSR to stack on entry to noreturn functions · e25e458d
  Tim Northover authored Apr 07, 2018
  e25e458d
- Revert "ARM: Do not spill CSR to stack on entry to noreturn functions" · de5f1965
  Vitaly Buka authored Apr 07, 2018
  de5f1965
Apr 06, 2018
- [StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic. · 13b83310
  Matt Davis authored Apr 06, 2018
  13b83310
- [CodeGen] Change std::sort to llvm::sort in response to r327219 · e92f0cfe
  Mandeep Singh Grang authored Apr 06, 2018
  e92f0cfe
- [MIR] Add support for MachineFrameInfo::LocalFrameSize · 537d7eee
  Francis Visoiu Mistrih authored Apr 06, 2018
  537d7eee
Apr 05, 2018
- ARM: Do not spill CSR to stack on entry to noreturn functions · b30388bf
  Tim Northover authored Apr 05, 2018
  b30388bf
- [DAGCombine] Revert r329160 · 0e7deb81
  Sam Parker authored Apr 05, 2018
  0e7deb81
- [MIR-Canon] Fixing warnings in Non-assert builds. · 8afc9936
  Puyan Lotfi authored Apr 05, 2018
  8afc9936
- [MIR-Canon] Improving performance by switching to named vregs. · d6f7313c
  Puyan Lotfi authored Apr 05, 2018
  d6f7313c
- [MIR-Canon] Adding support for multi-def -> user distance reduction. · 26c504fe
  Puyan Lotfi authored Apr 05, 2018
  26c504fe
Apr 04, 2018
- [MachineOutliner] Add `useMachineOutliner` target hook · bccd18b8
  Jessica Paquette authored Apr 04, 2018
  bccd18b8
- Fix build breakage from r329201 · 0cc0306a
  Pavel Labath authored Apr 04, 2018
  0cc0306a
- Re-commit r329179 after fixing build&test issues · 6088c234
  Pavel Labath authored Apr 04, 2018
  6088c234
- Revert r329179 (and follow-up unsuccessful fix attempts 329184, 329186); it doesn't build. · 55fcd07d
  Nico Weber authored Apr 04, 2018
  55fcd07d
- Attempt to fix bots more after r329179. · be6a9b6d
  Nico Weber authored Apr 04, 2018
  be6a9b6d
- Attempt to fix bots after r329179. · 7e654e32
  Nico Weber authored Apr 04, 2018
  7e654e32
- [CodeGen] Generate DWARF v5 Accelerator Tables · 69baab10
  Pavel Labath authored Apr 04, 2018
  69baab10
- [DAGCombine] Improve ReduceLoadWidth for SRL · 7ec722d6
  Sam Parker authored Apr 04, 2018
  7ec722d6
Apr 03, 2018
- [MachineOutliner][NFC] Make outlined functions have internal linkage · d506bf8e
  Jessica Paquette authored Apr 03, 2018
  d506bf8e
- [CodeGen]Add NoVRegs property on PostRASink and ShrinkWrap · 7ab1b32b
  Jun Bum Lim authored Apr 03, 2018
  7ab1b32b
- Adding optional Name parameter to createVirtualRegister and createGenericVirtualRegister. · 764b386e
  Puyan Lotfi authored Apr 03, 2018
  764b386e
- Align stubs for external and common global variables to pointer size. · 8c58750c
  Rafael Espindola authored Apr 02, 2018
  8c58750c
Apr 02, 2018
- [dsymutil] Upstream emitting of papertrail warnings. · 9e3e7a99
  Jonas Devlieghere authored Apr 02, 2018
  9e3e7a99
Mar 31, 2018
- [DAGCombine] (float)((int) f) --> ftrunc (PR36617) · 6124cae8
  Sanjay Patel authored Mar 31, 2018
  6124cae8
- [MIR-Canon] Adding support for local idempotent instruction hoisting. · 57c4f38c
  Puyan Lotfi authored Mar 31, 2018
  57c4f38c
- Fix a bunch of typoes. NFC · 956ee797
  Fangrui Song authored Mar 30, 2018
  956ee797
Mar 30, 2018
- [MIR] Adding support for Named Virtual Registers in MIR. · 399b46c9
  Puyan Lotfi authored Mar 30, 2018
  399b46c9
- [BlockPlacement] Disable block placement tail duplciation in structured CFG. · 1a8c6776
  Tim Shen authored Mar 30, 2018
  1a8c6776