Commits · c060945b23a1c54d4b2a053ff4b093a2277b303d · Lorenzo Albano / LLVM bpEVL · GitLab

Apr 06, 2021
- Replace calls to IntrinsicInst::Create with CallInst::Create [nfc] · 4bf8985f
  Philip Reames authored Apr 06, 2021
  4bf8985f
- Use AssumeInst in a few more places [nfc] · 908215b3
  Philip Reames authored Apr 06, 2021
  908215b3
- [NVPTX] Handle bitcast and ASC(101) when trying to avoid argument copy. · d0615a93
  Artem Belevich authored Apr 01, 2021
  d0615a93
- Plumb AssumeInst through operand bundle apis [nfc] · 9ef6aa02
  Philip Reames authored Apr 06, 2021
  9ef6aa02
- [ASan][RISCV] Fix RISC-V memory mapping · 0c3bc1f3
  Luís Marques authored Apr 06, 2021
  0c3bc1f3
- [PowerPC] Materialize 34-bit constants with pli directly · bd6033ec
  Amy Kwan authored Apr 06, 2021
  bd6033ec
- [NewPM] Fix -Wunused-lambda-capture in -DLLVM_ENABLE_ASSERTIONS=off builds after D91327 · a7ef45bc
  Fangrui Song authored Apr 06, 2021
  
  a7ef45bc
- More precisely type code used for gc.relocate assertions [nfc] · fb41cae0
  Philip Reames authored Apr 06, 2021
  
  fb41cae0
- Add a subclass of IntrinsicInst for llvm.assume [nfc] · a6d2a8d6
  Philip Reames authored Apr 06, 2021
  a6d2a8d6
- [GVN] Add missing ICF update · 4e83e59e
  Arthur Eubanks authored Apr 05, 2021
  4e83e59e
- [SimplifyInst] Use correct type for GEPs with vector indices. · 4059c1c3
  Florian Hahn authored Apr 06, 2021
  4059c1c3
- [RISCV] Add helper function to share some of the code for isel of vector load/store intrinsics. · 3ae03f67
  Craig Topper authored Apr 05, 2021
  3ae03f67
- [AMDGPU] SIFoldOperands: use isUseMIInFoldList. NFC. · 8f798566
  Jay Foad authored Apr 06, 2021
  
  8f798566
- Pass -fcrash-diagnostics-dir along to LLVM · 04b3c8c5
  Paul Robinson authored Mar 23, 2021
  04b3c8c5
- [AIX][TLS] Add support for TLS variables to XCOFF object writer · f98567b3
  Victor Huang authored Apr 06, 2021
  f98567b3
- [X86][SSE] canonicalizeShuffleWithBinOps - add MOVSD/MOVSS handling. · 53283cc2
  Simon Pilgrim authored Apr 06, 2021
  
  53283cc2
- Move GCRelocateInst and GCResultInst to IntrinsicInst.h [nfc] · 21d48399
  Philip Reames authored Apr 06, 2021
  21d48399
- AMDGPU: Add isBranch=1 to SOPP branch instructions · 84401294
  Konstantin Zhuravlyov authored Apr 06, 2021
  84401294
- Remove last remnants of PR49607 migration [NFC] · 52ecd94c
  Philip Reames authored Apr 06, 2021
  52ecd94c
- Revert "[IR] Ignore bitcasts of function pointers which are only used as... · fb6a5237
  Jan Svoboda authored Apr 06, 2021
  fb6a5237
- Avoid unused variable warning in Release builds · ce4acb01
  Benjamin Kramer authored Apr 06, 2021
  
  ce4acb01
- [AMDGPU] SIFoldOperands: use MachineRegisterInfo::hasOneNonDBGUser · efc7bf27
  Jay Foad authored Apr 06, 2021
  efc7bf27
- [AMDGPU] SIFoldOperands: use range-based loops and make_early_inc_range · 005dcd19
  Jay Foad authored Apr 06, 2021
  005dcd19
- [AMDGPU] SIFoldOperands: rename tryFoldInst to tryFoldCndMask · ce9cca6c
  Jay Foad authored Mar 31, 2021
  ce9cca6c
- [AMDGPU] SIFoldOperands: use getVRegDef instead of getUniqueVRegDef · cf4f5292
  Jay Foad authored Mar 31, 2021
  cf4f5292
- [AMDGPU][SDag] Add IMG init also for image_gather4 instructions · e9608a84
  Jay Foad authored Apr 06, 2021
  e9608a84
- [LoopVectorize] Add strict in-order reduction support for fixed-width vectorization · 7344f3d3
  Kerry McLaughlin authored Apr 06, 2021
  7344f3d3
- [X86] Improve optimizeCompareInstr for signed comparisons after ANDN instructions · 1dcb5b5e
  Simon Pilgrim authored Apr 06, 2021
  1dcb5b5e
- [InstCombine] Fold `((X - Y) - Z)` to `X - (Y + Z)` (PR49858) · 31d219d2
  Roman Lebedev authored Apr 06, 2021
  31d219d2
- LoopFlatten - CanWidenIV - Fix uninitialized variable warnings and use for-range loop. NFCI. · b8aba76a
  Simon Pilgrim authored Apr 06, 2021
  b8aba76a
- [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text · 82b3e28e
  Abhina Sreeskantharajan authored Apr 06, 2021
  82b3e28e
- [LoopVectorize] Change the identity element for FAdd · 857b8a73
  Kerry McLaughlin authored Apr 06, 2021
  857b8a73
- [VPlan] Print VPValue operands for VPWidenPHI if possible. · a6b06b78
  Florian Hahn authored Apr 06, 2021
  a6b06b78
- [AMDGPU][MC][GFX9] Corrected SMEM decoding · 3eadcb86
  Dmitry Preobrazhensky authored Apr 06, 2021
  3eadcb86
- [CostModel][X86] Improve accuracy of vXi8 multiply reduction costs · 201877d5
  Simon Pilgrim authored Apr 06, 2021
  201877d5
- [IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction · 167ea67d
  madhur13490 authored Mar 18, 2021
  167ea67d
- [KnownBits] Rename KnownBits::computeForMul to KnownBits::mul. NFCI. · ddbb5873
  Simon Pilgrim authored Mar 25, 2021
  ddbb5873
- [AArch64] Default to zero-cycle-zeroing FP registers · d5f1131c
  Sjoerd Meijer authored Apr 06, 2021
  d5f1131c
- [AArch64] Use 64-bit movi for zeroing halfs/floats · ef05b08c
  Sjoerd Meijer authored Apr 01, 2021
  ef05b08c
- [NewPM] Fix unused lambda capture build error · 98742e42
  Yevgeny Rouban authored Apr 06, 2021
  98742e42