Commits · c193a689b475f91e63adb25dc5855f7a7f068c9a · Lorenzo Albano / LLVM bpEVL · GitLab

Sep 14, 2020
- [SelectionDAG] Use Align/MaybeAlign in calls to getLoad/getStore/getExtLoad/getTruncStore. · c193a689
  Craig Topper authored Sep 14, 2020
  c193a689
- [AMDGPU] Add XDL resource to scheduling model · f859c30e
  Austin Kerbow authored Sep 13, 2020
  f859c30e
- [PowerPC] Implement Thread Local Storage Support for Local Exec · c0f199e5
  Kamau Bridgeman authored Sep 11, 2020
  c0f199e5
- [Legalize][ARM][X86] Add float legalization for VECREDUCE · 53f36f06
  Nikita Popov authored Sep 12, 2020
  53f36f06
- [ms] [llvm-ml] Add basic support for SEH, including PROC FRAME · 23a2b032
  Eric Astor authored Sep 14, 2020
  23a2b032
- [ms] [llvm-ml] Add support for size queries in MASM · 20201dc7
  Eric Astor authored Sep 14, 2020
  20201dc7
- [XCOFF][AIX] Handle TOC entries that could not be reached by positive range in small code model · 9868ea76
  jasonliu authored Sep 11, 2020
  9868ea76
- [AMDGPU] Don't cluster stores · c799f873
  Jay Foad authored Jun 03, 2020
  c799f873
- Assert we've found both vector types. NFCI. · 98eaacd7
  Simon Pilgrim authored Sep 14, 2020
  98eaacd7
- Don't dereference from a dyn_cast<>. NFCI. · 7109fc9e
  Simon Pilgrim authored Sep 14, 2020
  7109fc9e
- [ARM] Selects SSAT/USAT from correct LLVM IR · dd519bf0
  Meera Nakrani authored Sep 14, 2020
  dd519bf0
- [ARM][MVE] Tail-predication: check get.active.lane.mask's TC value · 676febc0
  Sjoerd Meijer authored Sep 09, 2020
  676febc0
- AMDGPU/GlobalISel Check for NoNaNsFPMath in isKnownNeverSNaN · 6e2a86ed
  Petar Avramovic authored Sep 14, 2020
  6e2a86ed
- AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands · 09b8871f
  Petar Avramovic authored Sep 14, 2020
  09b8871f
- [ARM] Fix so immediates and pc relative checks · 4946802c
  Simon Wallis authored Sep 14, 2020
  4946802c
Sep 13, 2020
- PPCInstrInfo: Fix readability-inconsistent-declaration-parameter-name clang-tidy warning · ce89eeee
  David Blaikie authored Sep 13, 2020
  ce89eeee
- Reland "[PowerPC] Implement instruction clustering for stores" · bec81dc6
  Qiu Chaofan authored Sep 13, 2020
  bec81dc6
- [X86] Use ISD::PARITY directly instead of emitting CTPOP and AND from... · 758732a3
  Craig Topper authored Sep 12, 2020
  758732a3
- [Hexagon] Avoid widening vectors with non-HVX element types · 9d300bc8
  Krzysztof Parzyszek authored Sep 12, 2020
  
  9d300bc8
Sep 12, 2020
- [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand... · ad3d6f99
  Craig Topper authored Sep 12, 2020
  ad3d6f99
- [LV][ARM] Add preferInloopReduction target hook. · 74760bb0
  David Green authored Sep 12, 2020
  74760bb0
- [InstCombine][X86] Covert masked load/stores with (sign extended) bool vector... · 3170d548
  Simon Pilgrim authored Sep 12, 2020
  3170d548
- [MachineScheduler] Fix operand scheduling for pre/post-increment loads · 2e61cd12
  Evgeny Leviant authored Sep 12, 2020
  2e61cd12
- [ARM] Fixup single source mla reductions. · 6cfd38d0
  David Green authored Sep 12, 2020
  6cfd38d0
- [Intrinsics] define semantics for experimental fmax/fmin vector reductions · 3a8ea860
  Sanjay Patel authored Sep 12, 2020
  3a8ea860
- [InstCombine][X86] getNegativeIsTrueBoolVec - use ConstantExpr evaluators. NFCI. · 50ee0b99
  Simon Pilgrim authored Sep 12, 2020
  50ee0b99
- [ARM] Recognize "double extend" reduction patterns · c437446d
  David Green authored Sep 12, 2020
  c437446d
- [X86][SSE] lowerShuffleAsDecomposedShuffleBlend - support decomposed unpacks... · 35dc91ae
  Simon Pilgrim authored Sep 12, 2020
  35dc91ae
- [Power10] Enable the heuristic for Power10 and switch the sched model · 0680a3d5
  QingShan Zhang authored Sep 12, 2020
  0680a3d5
- [PowerPC] Set the mayRaiseFPException for FCMPUS/FCMPUD · 528554c3
  QingShan Zhang authored Sep 12, 2020
  528554c3
Sep 11, 2020
- [WebAssembly] Add assembly syntax for mutable globals · fa2a8acc
  Sam Clegg authored Sep 11, 2020
  fa2a8acc
- [X86] Keep variables from getDataLayout/getDebugLoc calls as const reference. NFCI. · 70a05ee2
  Simon Pilgrim authored Sep 11, 2020
  70a05ee2
- [MC] [Win64EH] Canonicalize ARM64 unwind opcodes · 700fbe59
  Martin Storsjö authored Sep 07, 2020
  700fbe59
- Remove unused variable introduce in 0448d11a causing build · 03539619
  Zarko Todorovski authored Sep 10, 2020
  03539619
- [AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR at -O0. · 0448d11a
  Amara Emerson authored Sep 10, 2020
  0448d11a
Sep 10, 2020
- [Hexagon] Split pair-based masked memops · 783e28a5
  Krzysztof Parzyszek authored Sep 10, 2020
  
  783e28a5
- [WebAssembly] Set unreachable as canonical to permit disassembly · 4252f300
  Dominic Chen authored Sep 10, 2020
  4252f300
- [ImplicitNullCheck] Handle instructions that preserve zero value · 46329f60
  Anna Thomas authored Sep 10, 2020
  46329f60
- [PPC][GlobalISel] Add initial GlobalIsel infrastructure · 009cd4e4
  Kit Barton authored Aug 17, 2020
  009cd4e4
- Mark FMOV constant materialization as being as cheap as a move. · 3d9c85e4
  Owen Anderson authored Sep 08, 2020
  3d9c85e4