Differential revision: https://reviews.llvm.org/D27098

llvm-svn: 287914

This is important for cases like:

  .sdata        : {
    *(.got.plt .got)
...
  }

That was not supported before as there was no way to get access to 
synthetic sections from script.

More details on review page.

Differential revision: https://reviews.llvm.org/D27040

llvm-svn: 287913

Broke the build on arm7 and aarch64.

llvm-svn: 287911

Summary:
This implements a simple buffer queue to manage a pre-allocated queue of
fixed-sized buffers to hold XRay records. We need this to support
Flight Data Recorder (FDR) mode. We also implement this as a sub-library
first to allow for development before actually using it in an
implementation.

Some important properties of the buffer queue:

- Thread-safe enqueueing/dequeueing of fixed-size buffers.
- Pre-allocation of buffers at construction.

Reviewers: majnemer, rSerge, echristo

Subscribers: mehdi_amini, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D26232

llvm-svn: 287910

llvm-svn: 287909

llvm-svn: 287908

Differential Revision: https://reviews.llvm.org/D27069

llvm-svn: 287905

[DAGCombine] Teach DAG combine that if both inputs of a vselect are the same, then the condition doesn't matter and the vselect can be removed.

Selects with scalar condition already handle this correctly.

llvm-svn: 287904

I'd like to teach DAG combine to remove vselects where both sides are identical and these tests were in the way of that.

llvm-svn: 287903

GCD queues can be suspended and resumed with dispatch_suspend and dispatch_resume. We need to add synchronization between the call to dispatch_resume and any subsequent executions of blocks in the queue that was resumed. We already have an Acquire(q) before the block executes, so this patch just adds the Release(q) in an interceptor of dispatch_resume.

Differential Revision: https://reviews.llvm.org/D27112

llvm-svn: 287902

llvm-svn: 287901

This patch changes the error message from

  too many errors emitted, stopping now

to

  too many errors emitted, stopping now (use -error-limit=0 to see all errors)

Thanks for Sean for the suggestion!

llvm-svn: 287900

Differential Revision: https://reviews.llvm.org/D27065

llvm-svn: 287899

llvm-svn: 287898

[AVX-512] Add tests demonstrating failure to generated masked instructions for VSHUFF32x4 and VSHUFI32x4 due to shuffle lowering widening elements.

llvm-svn: 287897

I'm considering doing some refactor there, so I am adding these to guard the
current behavior.

llvm-svn: 287896

llvm-svn: 287895

No functionality change. Found by clang-tidy's
performance-unnecessary-value-param.

llvm-svn: 287894

The line numbers come out slightly differently when the test is run with gcc-4.9
as a compiler. The test probably should not depend on that, but that is a
different story.

llvm-svn: 287893

No functional change.

llvm-svn: 287892

llvm-svn: 287891

No functionality change intended. Fix by clang-tidy's
performance-unnecessary-value-param check.

llvm-svn: 287890

llvm-svn: 287889

No functional change.

llvm-svn: 287888

Test passes consistently, at least on linux.

llvm-svn: 287887

Vectorize UINT_TO_FP v2i32 -> v2f64 instead of scalarization (albeit still on the SIMD unit).

The codegen matches that generated by legalization (and is in fact used by AVX for UINT_TO_FP v4i32 -> v4f64), but has to be done in the x86 backend to account for legalization via 4i32.

Differential Revision: https://reviews.llvm.org/D26938

llvm-svn: 287886

Passing consistently now.

llvm-svn: 287885

The test has been passing for a while now.

llvm-svn: 287884

It consistently passes for linux-clang-i386, and linux-gcc-x86_64.

llvm-svn: 287883

Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances

llvm-svn: 287882

This test passes consistently on linux, so I am removing the overall XFAIL. If it
fails on your configuration, please put a targeted xfail instead (i'll add them
my self if I get any breakage emails).

llvm-svn: 287881

This refactors AdbClient interface in terms of std::chrono.

llvm-svn: 287880

This refactors the class implementations to use chrono. I'll follow this up with
a refactor of the class interface.

llvm-svn: 287879

[X86][AVX512DQVL] Add awareness of vcvtqq2ps and vcvtuqq2ps implicit zeroing of upper 64-bits of xmm result

llvm-svn: 287878

llvm-svn: 287877

llvm-svn: 287876

The bug arises during register allocation on i686 for
CMPXCHG8B instruction when base pointer is needed. CMPXCHG8B
needs 4 implicit registers (EAX, EBX, ECX, EDX) and a memory address,
plus ESI is reserved as the base pointer. With such constraints the only
way register allocator would do its job successfully is when the addressing
mode of the instruction requires only one register. If that is not the case
- we are emitting additional LEA instruction to compute the address.

It fixes PR28755.

Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>

Differential Revision: https://reviews.llvm.org/D25088

llvm-svn: 287875

Move the definitions of three variables out of the switch.

Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>

Differential Revision: https://reviews.llvm.org/D25192

llvm-svn: 287874

- It does not modify the input instruction
- Second operand of any address is always an Index Register,
  make sure we actually check for that, instead of a check for
  an immediate value

Patch by Alexander Ivchenko <alexander.ivchenko@intel.com>

Differential Revision: https://reviews.llvm.org/D24938

llvm-svn: 287873

(commit again after fixing the buildbot failures)
This adds various overloads of the following builtins to altivec.h:

    vec_neg
    vec_nabs
    vec_adde
    vec_addec
    vec_sube
    vec_subec
    vec_subc

Note that for vec_sub builtins on 32 bit integers, the semantics is similar to
what ISA describes for instructions like vsubecuq that work on quadwords: the
first operand is added to the one's complement of the second operand. (As
opposed to two's complement which I expected).

llvm-svn: 287872