llvm-svn: 187800

We do use a very small set of physical registers, so account for
them in the virtual register encoding between MachineInstr and MC

llvm-svn: 187799

.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

llvm-svn: 186820

llvm-svn: 185330

This makes it more consistent with the ZeroOrNegativeOneBooleanContent flag

llvm-svn: 185179

llvm-svn: 185178

llvm-svn: 185176

[NVPTX] Clean up comparison/select/convert patterns and factor out PTX instructions from their patterns

Test case is no breakage

llvm-svn: 185175

[NVPTX] Remove i8 register class.  PTX support for i8 (.b8, .u8, .s8) is rather poor and we're better off just ignoring it and letting LLVM expand all i8 ops out to i16.

llvm-svn: 185174

llvm-svn: 185171

llvm-svn: 182394

Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

llvm-svn: 174968

llvm-svn: 157885

This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.

The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

llvm-svn: 156196