- Mar 30, 2011
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Jay Foad authored
llvm-svn: 128535
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Benjamin Kramer authored
On x86 we now compile "if (a < 0 && b < 0)" into testl %edi, %esi js IF.THEN llvm-svn: 128496
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- Mar 29, 2011
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Benjamin Kramer authored
Fixes PR9569 and will hopefully make selfhost on ASLR-enabled systems more deterministic. llvm-svn: 128482
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Cameron Zwarich authored
vector types. This helps a lot with inlined functions when using the ARM soft float ABI. Fixes <rdar://problem/9184212>. llvm-svn: 128453
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- Mar 28, 2011
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Nick Lewycky authored
llvm-svn: 128413
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Jay Foad authored
llvm-svn: 128406
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Frits van Bommel authored
Add some debug output when -instcombine uses RAUW. This can make debug output for those cases much clearer since without this it only showed that the original instruction was removed, not what it was replaced with. llvm-svn: 128399
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- Mar 27, 2011
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Nick Lewycky authored
the subclass optional data. llvm-svn: 128388
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Benjamin Kramer authored
llvm-svn: 128380
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Nick Lewycky authored
removes one use of X which helps it pass the many hasOneUse() checks. In my analysis, this turns up very often where X = A >>exact B and that can't be simplified unless X has one use (except by increasing the lifetime of A which is generally a performance loss). llvm-svn: 128373
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- Mar 26, 2011
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Bill Wendling authored
llvm-svn: 128333
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Bill Wendling authored
There are two ways that a later store can comletely overlap a previous store: 1. They both start at the same offset, but the earlier store's size is <= the later's size, or 2. The earlier store's offset is > the later's offset, but it's offset + size doesn't extend past the later's offset + size. llvm-svn: 128332
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Cameron Zwarich authored
llvm-svn: 128331
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Bill Wendling authored
completely overlaps a previous store, thus mistakenly deleting that store. Check for this condition. llvm-svn: 128319
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- Mar 25, 2011
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Nick Lewycky authored
llvm-svn: 128257
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- Mar 24, 2011
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Cameron Zwarich authored
affect the generated code. llvm-svn: 128217
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Cameron Zwarich authored
void; it doesn't need to have a void type. llvm-svn: 128212
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Devang Patel authored
llvm-svn: 128211
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Cameron Zwarich authored
void return type. This fixes PR9487. llvm-svn: 128197
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Cameron Zwarich authored
llvm-svn: 128196
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Cameron Zwarich authored
use it later. I couldn't make a test that hits this with the current code. llvm-svn: 128195
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Cameron Zwarich authored
llvm-svn: 128194
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- Mar 23, 2011
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Cameron Zwarich authored
that were hit in practice. llvm-svn: 128146
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- Mar 22, 2011
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Anders Carlsson authored
llvm-svn: 128068
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- Mar 21, 2011
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Devang Patel authored
llvm-svn: 128030
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Anders Carlsson authored
llvm-svn: 127997
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Anders Carlsson authored
As suggested by Nick Lewycky, ignore debugging intrinsics when trying to decide whether a destructor is empty or not. llvm-svn: 127985
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Nick Lewycky authored
llvm-svn: 127984
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Evan Cheng authored
Re-apply r127953 with fixes: eliminate empty return block if it has no predecessors; update dominator tree if cfg is modified. llvm-svn: 127981
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- Mar 20, 2011
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Anders Carlsson authored
llvm-svn: 127976
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Anders Carlsson authored
llvm-svn: 127975
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Anders Carlsson authored
llvm-svn: 127974
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Anders Carlsson authored
Add an optimization to GlobalOpt that eliminates calls to __cxa_atexit, if the function passed is empty. llvm-svn: 127970
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- Mar 19, 2011
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Daniel Dunbar authored
to canonicalize IR", it broke a lot of things. llvm-svn: 127954
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Evan Cheng authored
to have single return block (at least getting there) for optimizations. This is general goodness but it would prevent some tailcall optimizations. One specific case is code like this: int f1(void); int f2(void); int f3(void); int f4(void); int f5(void); int f6(void); int foo(int x) { switch(x) { case 1: return f1(); case 2: return f2(); case 3: return f3(); case 4: return f4(); case 5: return f5(); case 6: return f6(); } } => LBB0_2: ## %sw.bb callq _f1 popq %rbp ret LBB0_3: ## %sw.bb1 callq _f2 popq %rbp ret LBB0_4: ## %sw.bb3 callq _f3 popq %rbp ret This patch teaches codegenprep to duplicate returns when the return value is a phi and where the phi operands are produced by tail calls followed by an unconditional branch: sw.bb7: ; preds = %entry %call8 = tail call i32 @f5() nounwind br label %return sw.bb9: ; preds = %entry %call10 = tail call i32 @f6() nounwind br label %return return: %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ] ret i32 %retval.0 This allows codegen to generate better code like this: LBB0_2: ## %sw.bb jmp _f1 ## TAILCALL LBB0_3: ## %sw.bb1 jmp _f2 ## TAILCALL LBB0_4: ## %sw.bb3 jmp _f3 ## TAILCALL rdar://9147433 llvm-svn: 127953
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Devang Patel authored
If an AllocaInst referred by DbgDeclareInst is used by a LoadInst then the LoadInst should also get a corresponding llvm.dbg.value intrinsic. llvm-svn: 127924
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Devang Patel authored
llvm-svn: 127923
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Devang Patel authored
llvm-svn: 127922
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- Mar 18, 2011
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Andrew Trick authored
llvm-svn: 127842
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Andrew Trick authored
SCEV may generate expressions composed of multiple pointers, which can lead to invalid GEP expansion. Until we can teach SCEV to follow strict pointer rules, make sure no bad GEPs creep into IR. Fixes rdar://problem/9038671. llvm-svn: 127839
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