This replaces use of std::error_code and ErrorOr in the ORC RPC support library
with Error and Expected. This required updating the OrcRemoteTarget API, Client,
and server code, as well as updating the Orc C API.

This patch also fixes several instances where Errors were dropped.

llvm-svn: 267457

Use the operand for how long to wait. This is somewhat
distasteful, since it would be better to just emit s_nop
with the right argument in the first place. This would require
changing TII::insertNoop to emit N operands, which would be easy.
Slightly more problematic is the post-RA scheduler and hazard recognizer
represent nops as a single null node, and would require inventing
another way of representing N nops.

llvm-svn: 267456

llvm-svn: 267455

types. Patch by Erik Pilkington!

llvm-svn: 267454

classes of an argument to use CXXRecordDecl::forallBases. Fix forallBases to
only visit each base class once.

llvm-svn: 267453

llvm-svn: 267452

llvm-svn: 267451

llvm-svn: 267450

Also reorder case to match enum order

llvm-svn: 267449

from working with reference types.

llvm-svn: 267448

Currently, the UBSan docs make it sound like the object-size sanitizer
will only detect out-of-bounds reads/writes. It also catches some
operations that don't necessarily access memory (invalid downcasts,
calls of methods on invalid pointers, ...). This patch adds a note
about this behavior in the docs.

llvm-svn: 267447

I have prepared some patches for LLVM OpenMP runtime, mostly addressing
ARMv8 support. Before I upstream them, I must address legal issues that
arose around my planned contribution. I was advised that before I send any
substantial commit, I need to make sure that LICENSE.txt file in the projects
repository contains a statement submitted by ARM, similar to the one provided
by Intel (see "a license agreement from the copyright/patent holders"). This is
the same situation as with top-level LLVM project: ARM has provided the same
statement in http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/ARM/LICENSE.TXT file.

Patch by Paul Osmialowski

Differential Revision: http://reviews.llvm.org/D19319

llvm-svn: 267446

  Additive expressions can have constant factors too that we can extract
  and thereby simplify the internal representation. For now we do
  compute the gcd of all constant factors but only extract the same
  (possibly negated) factor if there is one.

llvm-svn: 267445

preserve any deduced types from a failed deduction to a subsequent attempt at
deduction. Patch by Erik Pilkington!

llvm-svn: 267444

llvm-svn: 267443

  Before, we checked all GEPs in a statement in order to derive
  out-of-bound assumptions. However, this can not only introduce new
  parameters but it is also not clear what we can learn from GEPs that
  are not immediately used in a memory accesses inside the SCoP. As this
  case is very rare, no actual change in the behaviour is expected.

llvm-svn: 267442

  Before, assumptions derived from llvm.assume could reference new
  parameters that were not known to the SCoP before. These were neither
  beneficial to the representation nor to the user that reads the
  emitted remark. Now we project them out and keep only user assumptions
  on known parameters. Nevertheless, the new parameters are still part
  of the SCoPs parameter space as the SCEVAffinator currently adds them
  on demand.

llvm-svn: 267441

There has been much recent confusion about the partition in the lattice between constant and non-constant values.  Hopefully, documenting this will prevent confusion going forward.

llvm-svn: 267440

This function handled both unary and binary operators.  Cloning and specializing leads to much easier to follow code with minimal duplicatation.

llvm-svn: 267438

Fix early exit from linkInModule. IRMover::move returns false on
success and true on error.

Add a few more cases of merged common linkage variables with
different sizes and alignments.

llvm-svn: 267437

llvm-svn: 267436

Remember to svn add the new file.

llvm-svn: 267435

llvm-svn: 267434

Do not mark them as modifying any of the volatile registers by default.

llvm-svn: 267433

llvm-svn: 267432

This fixes a number of endianness issues as well as an ODR
violation that hopefully causes everything to be happy.

llvm-svn: 267431

llvm-svn: 267430

llvm-svn: 267429

It also seems to be unused. Get rid of it.
Thanks to Rafael for pointing out.

llvm-svn: 267428

Until PR27449 (https://llvm.org/bugs/show_bug.cgi?id=27449) is fixed in
clang this warning is pointless, since ASTFileSignatures will change
randomly when a module is rebuilt.

rdar://problem/25610919

llvm-svn: 267427

llvm-svn: 267426

[Clang][Builtin][AVX512]Adding k-register logic intrinsics KAND, KANDN, KOR, KORTEST, KXNOR, KXOR, KUNPACK instruction set.

Differential Revision: http://reviews.llvm.org/D19466

llvm-svn: 267425

Previously findClosestSuitableAluInstr was only considering the base register when checking the current instruction for suitability. Expand check to consider the offset if the offset is a register.

llvm-svn: 267424

  The new handling is consistent with the remaining code, e.g., we do
  not create a new parameter id for each lookup call but copy an
  existing one. Additionally, we now use the implicit order defined by
  the Parameters set instead of an explicit one defined in a map.

llvm-svn: 267423

Differential revision: http://reviews.llvm.org/D19480

llvm-svn: 267422

tracked by:
https://llvm.org/bugs/show_bug.cgi?id=27515

llvm-svn: 267421

visitAND, when folding and (load) forgets to check which output of
an indexed load is involved, happily folding the updated address
output on the following testcase:

target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

%typ = type { i32, i32 }

define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) {
  %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1
  %1 = load i32, i32* %b, align 4
  %2 = ptrtoint i32* %b to i64
  %3 = and i64 %2, -35184372088833
  %4 = inttoptr i64 %3 to i32*
  %_msld = load i32, i32* %4, align 4
  %zzz = add i32 %1,  %_msld
  ret i32 %zzz
}

Fix this by checking ResNo.

I've found a few more places that currently neglect to check for
indexed load, and tightened them up as well, but I don't have test
cases for them.  In fact, they might not be triggerable at all,
at least with current targets.  Still, better safe than sorry.

Differential Revision: http://reviews.llvm.org/D19202

llvm-svn: 267420

Commit r267137 was the reason for failing tests in LLVM test suite.

llvm-svn: 267419

Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...

llvm-svn: 267418

llvm-svn: 267417