VirtRegRewriter.cpp

        if (!VRM.isSpillSlotUsed(SS)) {
          MFI->RemoveStackObject(SS);
          ++NumDSS;
        }

    return true;
  }

private:

  /// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
  /// a scratch register is available.
  ///     xorq  %r12<kill>, %r13
  ///     addq  %rax, -184(%rbp)
  ///     addq  %r13, -184(%rbp)
  /// ==>
  ///     xorq  %r12<kill>, %r13
  ///     movq  -184(%rbp), %r12
  ///     addq  %rax, %r12
  ///     addq  %r13, %r12
  ///     movq  %r12, -184(%rbp)
  bool OptimizeByUnfold2(unsigned VirtReg, int SS,
                         MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator &MII,
                         std::vector<MachineInstr*> &MaybeDeadStores,
                         AvailableSpills &Spills,
                         BitVector &RegKills,
                         std::vector<MachineOperand*> &KillOps,
                         VirtRegMap &VRM) {

    MachineBasicBlock::iterator NextMII = next(MII);
    if (NextMII == MBB.end())
      return false;

    if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
      return false;

    // Now let's see if the last couple of instructions happens to have freed up
    // a register.
    const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
    unsigned PhysReg = FindFreeRegister(MII, MBB, RC, TRI, AllocatableRegs);
    if (!PhysReg)
      return false;

    MachineFunction &MF = *MBB.getParent();
    TRI = MF.getTarget().getRegisterInfo();
    MachineInstr &MI = *MII;
    if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, VRM))
      return false;

    // If the next instruction also folds the same SS modref and can be unfoled,
    // then it's worthwhile to issue a load from SS into the free register and
    // then unfold these instructions.
    if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM))
      return false;

    // Load from SS to the spare physical register.
    TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
    // This invalidates Phys.
    Spills.ClobberPhysReg(PhysReg);
    // Remember it's available.
    Spills.addAvailable(SS, PhysReg);
    MaybeDeadStores[SS] = NULL;

    // Unfold current MI.
    SmallVector<MachineInstr*, 4> NewMIs;
    if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
      assert(0 && "Unable unfold the load / store folding instruction!");
    assert(NewMIs.size() == 1);
    AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
    VRM.transferRestorePts(&MI, NewMIs[0]);
    MII = MBB.insert(MII, NewMIs[0]);
    InvalidateKills(MI, TRI, RegKills, KillOps);
    VRM.RemoveMachineInstrFromMaps(&MI);
    MBB.erase(&MI);
    ++NumModRefUnfold;

    // Unfold next instructions that fold the same SS.
    do {
      MachineInstr &NextMI = *NextMII;
      NextMII = next(NextMII);
      NewMIs.clear();
      if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
        assert(0 && "Unable unfold the load / store folding instruction!");
      assert(NewMIs.size() == 1);
      AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg);
      VRM.transferRestorePts(&NextMI, NewMIs[0]);
      MBB.insert(NextMII, NewMIs[0]);
      InvalidateKills(NextMI, TRI, RegKills, KillOps);
      VRM.RemoveMachineInstrFromMaps(&NextMI);
      MBB.erase(&NextMI);
      ++NumModRefUnfold;
    } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, VRM));

    // Store the value back into SS.
    TII->storeRegToStackSlot(MBB, NextMII, PhysReg, true, SS, RC);
    MachineInstr *StoreMI = prior(NextMII);
    VRM.addSpillSlotUse(SS, StoreMI);
    VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);

    return true;
  }

  /// OptimizeByUnfold - Turn a store folding instruction into a load folding
  /// instruction. e.g.
  ///     xorl  %edi, %eax
  ///     movl  %eax, -32(%ebp)
  ///     movl  -36(%ebp), %eax
  ///     orl   %eax, -32(%ebp)
  /// ==>
  ///     xorl  %edi, %eax
  ///     orl   -36(%ebp), %eax
  ///     mov   %eax, -32(%ebp)
  /// This enables unfolding optimization for a subsequent instruction which will
  /// also eliminate the newly introduced store instruction.
  bool OptimizeByUnfold(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator &MII,
                        std::vector<MachineInstr*> &MaybeDeadStores,
                        AvailableSpills &Spills,
                        BitVector &RegKills,
                        std::vector<MachineOperand*> &KillOps,
                        VirtRegMap &VRM) {
    MachineFunction &MF = *MBB.getParent();
    MachineInstr &MI = *MII;
    unsigned UnfoldedOpc = 0;
    unsigned UnfoldPR = 0;
    unsigned UnfoldVR = 0;
    int FoldedSS = VirtRegMap::NO_STACK_SLOT;
    VirtRegMap::MI2VirtMapTy::const_iterator I, End;
    for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
      // Only transform a MI that folds a single register.
      if (UnfoldedOpc)
        return false;
      UnfoldVR = I->second.first;
      VirtRegMap::ModRef MR = I->second.second;
      // MI2VirtMap be can updated which invalidate the iterator.
      // Increment the iterator first.
      ++I; 
      if (VRM.isAssignedReg(UnfoldVR))
        continue;
      // If this reference is not a use, any previous store is now dead.
      // Otherwise, the store to this stack slot is not dead anymore.
      FoldedSS = VRM.getStackSlot(UnfoldVR);
      MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
      if (DeadStore && (MR & VirtRegMap::isModRef)) {
        unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
        if (!PhysReg || !DeadStore->readsRegister(PhysReg))
          continue;
        UnfoldPR = PhysReg;
        UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
                                                      false, true);
      }
    }

    if (!UnfoldedOpc) {
      if (!UnfoldVR)
        return false;

      // Look for other unfolding opportunities.
      return OptimizeByUnfold2(UnfoldVR, FoldedSS, MBB, MII,
                               MaybeDeadStores, Spills, RegKills, KillOps, VRM);
    }

    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
      MachineOperand &MO = MI.getOperand(i);
      if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
        continue;
      unsigned VirtReg = MO.getReg();
      if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
        continue;
      if (VRM.isAssignedReg(VirtReg)) {
        unsigned PhysReg = VRM.getPhys(VirtReg);
        if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
          return false;
      } else if (VRM.isReMaterialized(VirtReg))
        continue;
      int SS = VRM.getStackSlot(VirtReg);
      unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
      if (PhysReg) {
        if (TRI->regsOverlap(PhysReg, UnfoldPR))
          return false;
        continue;
      }
      if (VRM.hasPhys(VirtReg)) {
        PhysReg = VRM.getPhys(VirtReg);
        if (!TRI->regsOverlap(PhysReg, UnfoldPR))
          continue;
      }

      // Ok, we'll need to reload the value into a register which makes
      // it impossible to perform the store unfolding optimization later.
      // Let's see if it is possible to fold the load if the store is
      // unfolded. This allows us to perform the store unfolding
      // optimization.
      SmallVector<MachineInstr*, 4> NewMIs;
      if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
        assert(NewMIs.size() == 1);
        MachineInstr *NewMI = NewMIs.back();
        NewMIs.clear();
        int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
        assert(Idx != -1);
        SmallVector<unsigned, 1> Ops;
        Ops.push_back(Idx);
        MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
        if (FoldedMI) {
          VRM.addSpillSlotUse(SS, FoldedMI);
          if (!VRM.hasPhys(UnfoldVR))
            VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
          VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
          MII = MBB.insert(MII, FoldedMI);
          InvalidateKills(MI, TRI, RegKills, KillOps);
          VRM.RemoveMachineInstrFromMaps(&MI);
          MBB.erase(&MI);
          MF.DeleteMachineInstr(NewMI);
          return true;
        }
        MF.DeleteMachineInstr(NewMI);
      }
    }

    return false;
  }

  /// CommuteToFoldReload -
  /// Look for
  /// r1 = load fi#1
  /// r1 = op r1, r2<kill>
  /// store r1, fi#1
  ///
  /// If op is commutable and r2 is killed, then we can xform these to
  /// r2 = op r2, fi#1
  /// store r2, fi#1
  bool CommuteToFoldReload(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator &MII,
                           unsigned VirtReg, unsigned SrcReg, int SS,
                           AvailableSpills &Spills,
                           BitVector &RegKills,
                           std::vector<MachineOperand*> &KillOps,
                           const TargetRegisterInfo *TRI,
                           VirtRegMap &VRM) {
    if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
      return false;

    MachineFunction &MF = *MBB.getParent();
    MachineInstr &MI = *MII;
    MachineBasicBlock::iterator DefMII = prior(MII);
    MachineInstr *DefMI = DefMII;
    const TargetInstrDesc &TID = DefMI->getDesc();
    unsigned NewDstIdx;
    if (DefMII != MBB.begin() &&
        TID.isCommutable() &&
        TII->CommuteChangesDestination(DefMI, NewDstIdx)) {
      MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
      unsigned NewReg = NewDstMO.getReg();
      if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
        return false;
      MachineInstr *ReloadMI = prior(DefMII);
      int FrameIdx;
      unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
      if (DestReg != SrcReg || FrameIdx != SS)
        return false;
      int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
      if (UseIdx == -1)
        return false;
      unsigned DefIdx;
      if (!MI.isRegTiedToDefOperand(UseIdx, &DefIdx))
        return false;
      assert(DefMI->getOperand(DefIdx).isReg() &&
             DefMI->getOperand(DefIdx).getReg() == SrcReg);

      // Now commute def instruction.
      MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
      if (!CommutedMI)
        return false;
      SmallVector<unsigned, 1> Ops;
      Ops.push_back(NewDstIdx);
      MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
      // Not needed since foldMemoryOperand returns new MI.
      MF.DeleteMachineInstr(CommutedMI);
      if (!FoldedMI)
        return false;

      VRM.addSpillSlotUse(SS, FoldedMI);
      VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
      // Insert new def MI and spill MI.
      const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
      TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
      MII = prior(MII);
      MachineInstr *StoreMI = MII;
      VRM.addSpillSlotUse(SS, StoreMI);
      VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
      MII = MBB.insert(MII, FoldedMI);  // Update MII to backtrack.

      // Delete all 3 old instructions.
      InvalidateKills(*ReloadMI, TRI, RegKills, KillOps);
      VRM.RemoveMachineInstrFromMaps(ReloadMI);
      MBB.erase(ReloadMI);
      InvalidateKills(*DefMI, TRI, RegKills, KillOps);
      VRM.RemoveMachineInstrFromMaps(DefMI);
      MBB.erase(DefMI);
      InvalidateKills(MI, TRI, RegKills, KillOps);
      VRM.RemoveMachineInstrFromMaps(&MI);
      MBB.erase(&MI);

      // If NewReg was previously holding value of some SS, it's now clobbered.
      // This has to be done now because it's a physical register. When this
      // instruction is re-visited, it's ignored.
      Spills.ClobberPhysReg(NewReg);

      ++NumCommutes;
      return true;
    }

    return false;
  }

  /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
  /// the last store to the same slot is now dead. If so, remove the last store.
  void SpillRegToStackSlot(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator &MII,
                           int Idx, unsigned PhysReg, int StackSlot,
                           const TargetRegisterClass *RC,
                           bool isAvailable, MachineInstr *&LastStore,
                           AvailableSpills &Spills,
                           SmallSet<MachineInstr*, 4> &ReMatDefs,
                           BitVector &RegKills,
                           std::vector<MachineOperand*> &KillOps,
                           VirtRegMap &VRM) {

    TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
    MachineInstr *StoreMI = next(MII);
    VRM.addSpillSlotUse(StackSlot, StoreMI);
    DOUT << "Store:\t" << *StoreMI;

    // If there is a dead store to this stack slot, nuke it now.
    if (LastStore) {
      DOUT << "Removed dead store:\t" << *LastStore;
      ++NumDSE;
      SmallVector<unsigned, 2> KillRegs;
      InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs);
      MachineBasicBlock::iterator PrevMII = LastStore;
      bool CheckDef = PrevMII != MBB.begin();
      if (CheckDef)
        --PrevMII;
      VRM.RemoveMachineInstrFromMaps(LastStore);
      MBB.erase(LastStore);
      if (CheckDef) {
        // Look at defs of killed registers on the store. Mark the defs
        // as dead since the store has been deleted and they aren't
        // being reused.
        for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
          bool HasOtherDef = false;
          if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
            MachineInstr *DeadDef = PrevMII;
            if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
              // FIXME: This assumes a remat def does not have side
              // effects.
              VRM.RemoveMachineInstrFromMaps(DeadDef);
              MBB.erase(DeadDef);
              ++NumDRM;
            }
          }
        }
      }
    }

    LastStore = next(MII);

    // If the stack slot value was previously available in some other
    // register, change it now.  Otherwise, make the register available,
    // in PhysReg.
    Spills.ModifyStackSlotOrReMat(StackSlot);
    Spills.ClobberPhysReg(PhysReg);
    Spills.addAvailable(StackSlot, PhysReg, isAvailable);
    ++NumStores;
  }

  /// TransferDeadness - A identity copy definition is dead and it's being
  /// removed. Find the last def or use and mark it as dead / kill.
  void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
                        unsigned Reg, BitVector &RegKills,
                        std::vector<MachineOperand*> &KillOps,
                        VirtRegMap &VRM) {
    SmallPtrSet<MachineInstr*, 4> Seens;
    SmallVector<std::pair<MachineInstr*, int>,8> Refs;
    for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
           RE = RegInfo->reg_end(); RI != RE; ++RI) {
      MachineInstr *UDMI = &*RI;
      if (UDMI->getParent() != MBB)
        continue;
      DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
      if (DI == DistanceMap.end() || DI->second > CurDist)
        continue;
      if (Seens.insert(UDMI))
        Refs.push_back(std::make_pair(UDMI, DI->second));
    }

    if (Refs.empty())
      return;
    std::sort(Refs.begin(), Refs.end(), RefSorter());

    while (!Refs.empty()) {
      MachineInstr *LastUDMI = Refs.back().first;
      Refs.pop_back();

      MachineOperand *LastUD = NULL;
      for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
        MachineOperand &MO = LastUDMI->getOperand(i);
        if (!MO.isReg() || MO.getReg() != Reg)
          continue;
        if (!LastUD || (LastUD->isUse() && MO.isDef()))
          LastUD = &MO;
        if (LastUDMI->isRegTiedToDefOperand(i))
          break;
      }
      if (LastUD->isDef()) {
        // If the instruction has no side effect, delete it and propagate
        // backward further. Otherwise, mark is dead and we are done.
        const TargetInstrDesc &TID = LastUDMI->getDesc();
        if (TID.mayStore() || TID.isCall() || TID.isTerminator() ||
            TID.hasUnmodeledSideEffects()) {
          LastUD->setIsDead();
          break;
        }
        VRM.RemoveMachineInstrFromMaps(LastUDMI);
        MBB->erase(LastUDMI);
      } else {
        LastUD->setIsKill();
        RegKills.set(Reg);
        KillOps[Reg] = LastUD;
        break;
      }
    }
  }

  /// rewriteMBB - Keep track of which spills are available even after the
  /// register allocator is done with them.  If possible, avid reloading vregs.
  void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
                  LiveIntervals *LIs,
                  AvailableSpills &Spills, BitVector &RegKills,
                  std::vector<MachineOperand*> &KillOps) {

    DOUT << "\n**** Local spiller rewriting MBB '"
         << MBB.getBasicBlock()->getName() << "':\n";

    MachineFunction &MF = *MBB.getParent();
    
    // MaybeDeadStores - When we need to write a value back into a stack slot,
    // keep track of the inserted store.  If the stack slot value is never read
    // (because the value was used from some available register, for example), and
    // subsequently stored to, the original store is dead.  This map keeps track
    // of inserted stores that are not used.  If we see a subsequent store to the
    // same stack slot, the original store is deleted.
    std::vector<MachineInstr*> MaybeDeadStores;
    MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);

    // ReMatDefs - These are rematerializable def MIs which are not deleted.
    SmallSet<MachineInstr*, 4> ReMatDefs;

    // Clear kill info.
    SmallSet<unsigned, 2> KilledMIRegs;
    RegKills.reset();
    KillOps.clear();
    KillOps.resize(TRI->getNumRegs(), NULL);

    unsigned Dist = 0;
    DistanceMap.clear();
    for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
         MII != E; ) {
      MachineBasicBlock::iterator NextMII = next(MII);

      VirtRegMap::MI2VirtMapTy::const_iterator I, End;
      bool Erased = false;
      bool BackTracked = false;
      if (OptimizeByUnfold(MBB, MII,
                           MaybeDeadStores, Spills, RegKills, KillOps, VRM))
        NextMII = next(MII);

      MachineInstr &MI = *MII;

      if (VRM.hasEmergencySpills(&MI)) {
        // Spill physical register(s) in the rare case the allocator has run out
        // of registers to allocate.
        SmallSet<int, 4> UsedSS;
        std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
        for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
          unsigned PhysReg = EmSpills[i];
          const TargetRegisterClass *RC =
            TRI->getPhysicalRegisterRegClass(PhysReg);
          assert(RC && "Unable to determine register class!");
          int SS = VRM.getEmergencySpillSlot(RC);
          if (UsedSS.count(SS))
            assert(0 && "Need to spill more than one physical registers!");
          UsedSS.insert(SS);
          TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
          MachineInstr *StoreMI = prior(MII);
          VRM.addSpillSlotUse(SS, StoreMI);
          TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
          MachineInstr *LoadMI = next(MII);
          VRM.addSpillSlotUse(SS, LoadMI);
          ++NumPSpills;
        }
        NextMII = next(MII);
      }

      // Insert restores here if asked to.
      if (VRM.isRestorePt(&MI)) {
        std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
        for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
          unsigned VirtReg = RestoreRegs[e-i-1];  // Reverse order.
          if (!VRM.getPreSplitReg(VirtReg))
            continue; // Split interval spilled again.
          unsigned Phys = VRM.getPhys(VirtReg);
          RegInfo->setPhysRegUsed(Phys);

          // Check if the value being restored if available. If so, it must be
          // from a predecessor BB that fallthrough into this BB. We do not
          // expect:
          // BB1:
          // r1 = load fi#1
          // ...
          //    = r1<kill>
          // ... # r1 not clobbered
          // ...
          //    = load fi#1
          bool DoReMat = VRM.isReMaterialized(VirtReg);
          int SSorRMId = DoReMat
            ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
          const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
          unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
          if (InReg == Phys) {
            // If the value is already available in the expected register, save
            // a reload / remat.
            if (SSorRMId)
              DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1;
            else
              DOUT << "Reusing SS#" << SSorRMId;
            DOUT << " from physreg "
                 << TRI->getName(InReg) << " for vreg"
                 << VirtReg <<" instead of reloading into physreg "
                 << TRI->getName(Phys) << "\n";
            ++NumOmitted;
            continue;
          } else if (InReg && InReg != Phys) {
            if (SSorRMId)
              DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1;
            else
              DOUT << "Reusing SS#" << SSorRMId;
            DOUT << " from physreg "
                 << TRI->getName(InReg) << " for vreg"
                 << VirtReg <<" by copying it into physreg "
                 << TRI->getName(Phys) << "\n";

            // If the reloaded / remat value is available in another register,
            // copy it to the desired register.
            TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC);

            // This invalidates Phys.
            Spills.ClobberPhysReg(Phys);
            // Remember it's available.
            Spills.addAvailable(SSorRMId, Phys);

            // Mark is killed.
            MachineInstr *CopyMI = prior(MII);
            MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg);
            KillOpnd->setIsKill();
            UpdateKills(*CopyMI, TRI, RegKills, KillOps);

            DOUT << '\t' << *CopyMI;
            ++NumCopified;
            continue;
          }

          if (VRM.isReMaterialized(VirtReg)) {
            ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM);
          } else {
            const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
            TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC);
            MachineInstr *LoadMI = prior(MII);
            VRM.addSpillSlotUse(SSorRMId, LoadMI);
            ++NumLoads;
          }

          // This invalidates Phys.
          Spills.ClobberPhysReg(Phys);
          // Remember it's available.
          Spills.addAvailable(SSorRMId, Phys);

          UpdateKills(*prior(MII), TRI, RegKills, KillOps);
          DOUT << '\t' << *prior(MII);
        }
      }

      // Insert spills here if asked to.
      if (VRM.isSpillPt(&MI)) {
        std::vector<std::pair<unsigned,bool> > &SpillRegs =
          VRM.getSpillPtSpills(&MI);
        for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
          unsigned VirtReg = SpillRegs[i].first;
          bool isKill = SpillRegs[i].second;
          if (!VRM.getPreSplitReg(VirtReg))
            continue; // Split interval spilled again.
          const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
          unsigned Phys = VRM.getPhys(VirtReg);
          int StackSlot = VRM.getStackSlot(VirtReg);
          TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
          MachineInstr *StoreMI = next(MII);
          VRM.addSpillSlotUse(StackSlot, StoreMI);
          DOUT << "Store:\t" << *StoreMI;
          VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
        }
        NextMII = next(MII);
      }

      /// ReusedOperands - Keep track of operand reuse in case we need to undo
      /// reuse.
      ReuseInfo ReusedOperands(MI, TRI);
      SmallVector<unsigned, 4> VirtUseOps;
      for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
        MachineOperand &MO = MI.getOperand(i);
        if (!MO.isReg() || MO.getReg() == 0)
          continue;   // Ignore non-register operands.
        
        unsigned VirtReg = MO.getReg();
        if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
          // Ignore physregs for spilling, but remember that it is used by this
          // function.
          RegInfo->setPhysRegUsed(VirtReg);
          continue;
        }

        // We want to process implicit virtual register uses first.
        if (MO.isImplicit())
          // If the virtual register is implicitly defined, emit a implicit_def
          // before so scavenger knows it's "defined".
          VirtUseOps.insert(VirtUseOps.begin(), i);
        else
          VirtUseOps.push_back(i);
      }

      // Process all of the spilled uses and all non spilled reg references.
      SmallVector<int, 2> PotentialDeadStoreSlots;
      KilledMIRegs.clear();
      for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
        unsigned i = VirtUseOps[j];
        MachineOperand &MO = MI.getOperand(i);
        unsigned VirtReg = MO.getReg();
        assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
               "Not a virtual register?");

        unsigned SubIdx = MO.getSubReg();
        if (VRM.isAssignedReg(VirtReg)) {
          // This virtual register was assigned a physreg!
          unsigned Phys = VRM.getPhys(VirtReg);
          RegInfo->setPhysRegUsed(Phys);
          if (MO.isDef())
            ReusedOperands.markClobbered(Phys);
          unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
          MI.getOperand(i).setReg(RReg);
          MI.getOperand(i).setSubReg(0);
          if (VRM.isImplicitlyDefined(VirtReg))
            BuildMI(MBB, &MI, MI.getDebugLoc(),
                    TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
          continue;
        }
        
        // This virtual register is now known to be a spilled value.
        if (!MO.isUse())
          continue;  // Handle defs in the loop below (handle use&def here though)

        bool AvoidReload = false;
        if (LIs->hasInterval(VirtReg)) {
          LiveInterval &LI = LIs->getInterval(VirtReg);
          if (!LI.liveAt(LIs->getUseIndex(LI.beginNumber())))
            // Must be defined by an implicit def. It should not be spilled. Note,
            // this is for correctness reason. e.g.
            // 8   %reg1024<def> = IMPLICIT_DEF
            // 12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
            // The live range [12, 14) are not part of the r1024 live interval since
            // it's defined by an implicit def. It will not conflicts with live
            // interval of r1025. Now suppose both registers are spilled, you can
            // easily see a situation where both registers are reloaded before
            // the INSERT_SUBREG and both target registers that would overlap.
            AvoidReload = true;
        }

        bool DoReMat = VRM.isReMaterialized(VirtReg);
        int SSorRMId = DoReMat
          ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
        int ReuseSlot = SSorRMId;

        // Check to see if this stack slot is available.
        unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);

        // If this is a sub-register use, make sure the reuse register is in the
        // right register class. For example, for x86 not all of the 32-bit
        // registers have accessible sub-registers.
        // Similarly so for EXTRACT_SUBREG. Consider this:
        // EDI = op
        // MOV32_mr fi#1, EDI
        // ...
        //       = EXTRACT_SUBREG fi#1
        // fi#1 is available in EDI, but it cannot be reused because it's not in
        // the right register file.
        if (PhysReg && !AvoidReload &&
            (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
          const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
          if (!RC->contains(PhysReg))
            PhysReg = 0;
        }

        if (PhysReg && !AvoidReload) {
          // This spilled operand might be part of a two-address operand.  If this
          // is the case, then changing it will necessarily require changing the 
          // def part of the instruction as well.  However, in some cases, we
          // aren't allowed to modify the reused register.  If none of these cases
          // apply, reuse it.
          bool CanReuse = true;
          bool isTied = MI.isRegTiedToDefOperand(i);
          if (isTied) {
            // Okay, we have a two address operand.  We can reuse this physreg as
            // long as we are allowed to clobber the value and there isn't an
            // earlier def that has already clobbered the physreg.
            CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
              Spills.canClobberPhysReg(PhysReg);
          }
          
          if (CanReuse) {
            // If this stack slot value is already available, reuse it!
            if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
              DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
            else
              DOUT << "Reusing SS#" << ReuseSlot;
            DOUT << " from physreg "
                 << TRI->getName(PhysReg) << " for vreg"
                 << VirtReg <<" instead of reloading into physreg "
                 << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
            unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
            MI.getOperand(i).setReg(RReg);
            MI.getOperand(i).setSubReg(0);

            // The only technical detail we have is that we don't know that
            // PhysReg won't be clobbered by a reloaded stack slot that occurs
            // later in the instruction.  In particular, consider 'op V1, V2'.
            // If V1 is available in physreg R0, we would choose to reuse it
            // here, instead of reloading it into the register the allocator
            // indicated (say R1).  However, V2 might have to be reloaded
            // later, and it might indicate that it needs to live in R0.  When
            // this occurs, we need to have information available that
            // indicates it is safe to use R1 for the reload instead of R0.
            //
            // To further complicate matters, we might conflict with an alias,
            // or R0 and R1 might not be compatible with each other.  In this
            // case, we actually insert a reload for V1 in R1, ensuring that
            // we can get at R0 or its alias.
            ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
                                    VRM.getPhys(VirtReg), VirtReg);
            if (isTied)
              // Only mark it clobbered if this is a use&def operand.
              ReusedOperands.markClobbered(PhysReg);
            ++NumReused;

            if (MI.getOperand(i).isKill() &&
                ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {

              // The store of this spilled value is potentially dead, but we
              // won't know for certain until we've confirmed that the re-use
              // above is valid, which means waiting until the other operands
              // are processed. For now we just track the spill slot, we'll
              // remove it after the other operands are processed if valid.

              PotentialDeadStoreSlots.push_back(ReuseSlot);
            }

            // Mark is isKill if it's there no other uses of the same virtual
            // register and it's not a two-address operand. IsKill will be
            // unset if reg is reused.
            if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
              MI.getOperand(i).setIsKill();
              KilledMIRegs.insert(VirtReg);
            }

            continue;
          }  // CanReuse
          
          // Otherwise we have a situation where we have a two-address instruction
          // whose mod/ref operand needs to be reloaded.  This reload is already
          // available in some register "PhysReg", but if we used PhysReg as the
          // operand to our 2-addr instruction, the instruction would modify
          // PhysReg.  This isn't cool if something later uses PhysReg and expects
          // to get its initial value.
          //
          // To avoid this problem, and to avoid doing a load right after a store,
          // we emit a copy from PhysReg into the designated register for this
          // operand.
          unsigned DesignatedReg = VRM.getPhys(VirtReg);
          assert(DesignatedReg && "Must map virtreg to physreg!");

          // Note that, if we reused a register for a previous operand, the
          // register we want to reload into might not actually be
          // available.  If this occurs, use the register indicated by the
          // reuser.
          if (ReusedOperands.hasReuses())
            DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI, 
                                 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
          
          // If the mapped designated register is actually the physreg we have
          // incoming, we don't need to inserted a dead copy.
          if (DesignatedReg == PhysReg) {
            // If this stack slot value is already available, reuse it!
            if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
              DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
            else
              DOUT << "Reusing SS#" << ReuseSlot;
            DOUT << " from physreg " << TRI->getName(PhysReg)
                 << " for vreg" << VirtReg
                 << " instead of reloading into same physreg.\n";
            unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
            MI.getOperand(i).setReg(RReg);
            MI.getOperand(i).setSubReg(0);
            ReusedOperands.markClobbered(RReg);
            ++NumReused;
            continue;
          }
          
          const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
          RegInfo->setPhysRegUsed(DesignatedReg);
          ReusedOperands.markClobbered(DesignatedReg);
          TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);

          MachineInstr *CopyMI = prior(MII);
          UpdateKills(*CopyMI, TRI, RegKills, KillOps);

          // This invalidates DesignatedReg.
          Spills.ClobberPhysReg(DesignatedReg);
          
          Spills.addAvailable(ReuseSlot, DesignatedReg);
          unsigned RReg =
            SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
          MI.getOperand(i).setReg(RReg);
          MI.getOperand(i).setSubReg(0);
          DOUT << '\t' << *prior(MII);
          ++NumReused;
          continue;
        } // if (PhysReg)
        
        // Otherwise, reload it and remember that we have it.
        PhysReg = VRM.getPhys(VirtReg);
        assert(PhysReg && "Must map virtreg to physreg!");

        // Note that, if we reused a register for a previous operand, the
        // register we want to reload into might not actually be
        // available.  If this occurs, use the register indicated by the
        // reuser.
        if (ReusedOperands.hasReuses())
          PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI, 
                                 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
        
        RegInfo->setPhysRegUsed(PhysReg);
        ReusedOperands.markClobbered(PhysReg);
        if (AvoidReload)
          ++NumAvoided;
        else {
          if (DoReMat) {
            ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM);
          } else {
            const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
            TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
            MachineInstr *LoadMI = prior(MII);
            VRM.addSpillSlotUse(SSorRMId, LoadMI);
            ++NumLoads;
          }
          // This invalidates PhysReg.
          Spills.ClobberPhysReg(PhysReg);

          // Any stores to this stack slot are not dead anymore.
          if (!DoReMat)
            MaybeDeadStores[SSorRMId] = NULL;
          Spills.addAvailable(SSorRMId, PhysReg);
          // Assumes this is the last use. IsKill will be unset if reg is reused
          // unless it's a two-address operand.
          if (!MI.isRegTiedToDefOperand(i) &&
              KilledMIRegs.count(VirtReg) == 0) {
            MI.getOperand(i).setIsKill();
            KilledMIRegs.insert(VirtReg);
          }

          UpdateKills(*prior(MII), TRI, RegKills, KillOps);
          DOUT << '\t' << *prior(MII);
        }
        unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
        MI.getOperand(i).setReg(RReg);
        MI.getOperand(i).setSubReg(0);
      }

      // Ok - now we can remove stores that have been confirmed dead.
      for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
        // This was the last use and the spilled value is still available
        // for reuse. That means the spill was unnecessary!
        int PDSSlot = PotentialDeadStoreSlots[j];
        MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
        if (DeadStore) {
          DOUT << "Removed dead store:\t" << *DeadStore;
          InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
          VRM.RemoveMachineInstrFromMaps(DeadStore);
          MBB.erase(DeadStore);
          MaybeDeadStores[PDSSlot] = NULL;
          ++NumDSE;
        }
      }


      DOUT << '\t' << MI;


      // If we have folded references to memory operands, make sure we clear all
      // physical registers that may contain the value of the spilled virtual
      // register
      SmallSet<int, 2> FoldedSS;
      for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
        unsigned VirtReg = I->second.first;
        VirtRegMap::ModRef MR = I->second.second;
        DOUT << "Folded vreg: " << VirtReg << "  MR: " << MR;

        // MI2VirtMap be can updated which invalidate the iterator.
        // Increment the iterator first.
        ++I;
        int SS = VRM.getStackSlot(VirtReg);
        if (SS == VirtRegMap::NO_STACK_SLOT)
          continue;
        FoldedSS.insert(SS);
        DOUT << " - StackSlot: " << SS << "\n";
        
        // If this folded instruction is just a use, check to see if it's a
        // straight load from the virt reg slot.
        if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
          int FrameIdx;
          unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
          if (DestReg && FrameIdx == SS) {
            // If this spill slot is available, turn it into a copy (or nothing)
            // instead of leaving it as a load!
            if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
              DOUT << "Promoted Load To Copy: " << MI;
              if (DestReg != InReg) {
                const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
                TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
                MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
                unsigned SubIdx = DefMO->getSubReg();
                // Revisit the copy so we make sure to notice the effects of the
                // operation on the destreg (either needing to RA it if it's 
                // virtual or needing to clobber any values if it's physical).
                NextMII = &MI;
                --NextMII;  // backtrack to the copy.
                // Propagate the sub-register index over.
                if (SubIdx) {
                  DefMO = NextMII->findRegisterDefOperand(DestReg);
                  DefMO->setSubReg(SubIdx);
                }

                // Mark is killed.
                MachineOperand *KillOpnd = NextMII->findRegisterUseOperand(InReg);
                KillOpnd->setIsKill();

                BackTracked = true;
              } else {
                DOUT << "Removing now-noop copy: " << MI;
                // Unset last kill since it's being reused.
                InvalidateKill(InReg, TRI, RegKills, KillOps);
                Spills.disallowClobberPhysReg(InReg);
              }

              InvalidateKills(MI, TRI, RegKills, KillOps);
              VRM.RemoveMachineInstrFromMaps(&MI);
              MBB.erase(&MI);
              Erased = true;
              goto ProcessNextInst;
            }
          } else {
            unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
            SmallVector<MachineInstr*, 4> NewMIs;
            if (PhysReg &&
                TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
              MBB.insert(MII, NewMIs[0]);
              InvalidateKills(MI, TRI, RegKills, KillOps);
              VRM.RemoveMachineInstrFromMaps(&MI);
              MBB.erase(&MI);
              Erased = true;
              --NextMII;  // backtrack to the unfolded instruction.
              BackTracked = true;
              goto ProcessNextInst;
            }
          }
        }

        // If this reference is not a use, any previous store is now dead.
        // Otherwise, the store to this stack slot is not dead anymore.
        MachineInstr* DeadStore = MaybeDeadStores[SS];
        if (DeadStore) {
          bool isDead = !(MR & VirtRegMap::isRef);
          MachineInstr *NewStore = NULL;