llvm/lib/Target/ARM/ARMInstrInfo.td · 424601a9b328b3ce3301fa8718429ea9d21ec5d5 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Make RegList an ASM operand so that TableGen will generate code for it. This is · 424601a9
Bill Wendling authored Nov 08, 2010
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an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390
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424601a9