overload UserInInstr. Explicitly check Allocatable. The early exit in the
condition will mean the performance impact of the extra test should be
minimal.

llvm-svn: 113016

solve the root problem, but it corrects the bug in the code I added to
support legalizing in the case where the non-extended type is also legal.

llvm-svn: 112997

slot.

Teach it to also check for early clobbered aliases, and early clobber operands
following the current operand.

This fixes the miscompilation in PR8044 where EC registers eax and ecx were
being used for inputs.

llvm-svn: 112988

Original commit message:
Use the SSAUpdator to turn calls to eh.exception that are not in a
landing pad into uses of registers rather than loads from a stack
slot.  Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)

llvm-svn: 112952

Thanks Chris!

llvm-svn: 112900

llvm-svn: 112864

there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.

llvm-svn: 112861

llvm-svn: 112858

locally.

llvm-svn: 112845

llvm-svn: 112832

llvm-svn: 112830

Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code.

Spill intervals can be hidden using the "-rmf-intervals=virt-nospills*" option.

llvm-svn: 112811

llvm-svn: 112809

llvm-svn: 112807

llvm-svn: 112787

at them since they'd end up in the register weights list. Tell it to stop
doing that.

llvm-svn: 112756

This caused a miscompilation in WebKit where %RAX had conflicting defs when
RemoveCopyByCommutingDef was commuting a %EAX use.

llvm-svn: 112751

llvm-svn: 112746

physical register in a register class. Make sure to assert if the register
class is empty.

llvm-svn: 112743

llvm-svn: 112742

r112728 did this for fast regalloc.

llvm-svn: 112741

llvm-svn: 112728

llvm-svn: 112726

self host errors on clang-x86-64.

llvm-svn: 112719

landing pad into uses of registers rather than loads from a stack
slot.  Doesn't touch the 'orrible hack code - Bill needs to persuade
me harder :)

llvm-svn: 112702

This patch was developed on top of original patch by Artur Pietrek.

llvm-svn: 112678

llvm-svn: 112659

Reserved registers are unpredictable, and are treated as always live by machine
DCE.

Allocatable registers are never reserved, and can be used for virtual registers.

Unreserved, unallocatable registers can not be used for virtual registers, but
otherwise behave like a normal allocatable register. Most targets only have
the flag register in this set.

llvm-svn: 112649

llvm-svn: 112632

llvm-svn: 112631

Remember byval argument's frame index during argument lowering and use this info to emit debug info.
Fixes Radar 8367011.

llvm-svn: 112623

  1. Allocate them in the entry block of the function to enable function-wide
     re-use. The instructions to create them should be re-materializable, so
     there shouldn't be additional cost compared to creating them local
     to the basic blocks where they are used.
  2. Collect all of the frame index references for the function and sort them
     by the local offset referenced. Iterate over the sorted list to
     allocate the virtual base registers. This enables creation of base
     registers optimized for positive-offset access of frame references.
     (Note: This may be appropriate to later be a target hook to do the
     sorting in a target appropriate manner. For now it's done here for
     simplicity.)

llvm-svn: 112609

any more.  I plan to reimplement alloca promotion using SSAUpdater later.
It looks like Bill's URoR logic really always needs domtree, so the pass
now always asks for domtree info.

llvm-svn: 112597

llvm-svn: 112584

llvm-svn: 112583

llvm-svn: 112571

Eventually, we want to disable physreg coalescing completely, and let the
register allocator do its job using hints.

This option makes it possible to measure the impact of disabling physreg
coalescing.

llvm-svn: 112567

1) nuke ConstDataCoalSection, which is dead.
2) revise my previous patch for rdar://8018335,
  which was completely wrong.  Specifically, it doesn't 
  make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS,
  because it is for readonly data.  templates (it turns out)
  go to const_coal_nt.  The real fix for rdar://8018335 was
  to give ConstTextCoalSection a section kind of ReadOnly 
  instead of Text.

llvm-svn: 112496

llvm-svn: 112463

said (physical) register.

llvm-svn: 112461