array instead, since this is what the scheduler actually cares about.
And remove a check that is unnecessary, since it can assume that
SUnits isn't empty.

llvm-svn: 62362

llvm-svn: 62359

llvm-svn: 62358

CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.

llvm-svn: 62356

llvm-svn: 62341

llvm-svn: 62328

warning.

llvm-svn: 62327

Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

llvm-svn: 62312

llvm-svn: 62307

llvm-svn: 62298

llvm-svn: 62294

a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.

llvm-svn: 62291

llvm-svn: 62288

Validate dbg_* intrinsics before lowering them.

llvm-svn: 62286

llvm-svn: 62285

to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.

llvm-svn: 62284

loops, hoisting instructions all the way out in one step rather
than hoisting them one nest level at a time. Also, make a few
other code simplifications. This speeds up MachineLICM
by several fold.

llvm-svn: 62283

llvm-svn: 62279

llvm-svn: 62276

and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275

Use light weight DebugInfo object directly.

llvm-svn: 62269

previous commit.

llvm-svn: 62266

llvm-svn: 62262

llvm-svn: 62260

llvm-svn: 62256

llvm-svn: 62209

Removoe MachineModuleInfo methods (and related DebugInfoDesc class  hierarchy) that were used to handle debug info.

llvm-svn: 62199

Keep "has debug info" big in MachineModuleInfo to avoid circular dependency between AsmPrinter and CodeGen.

llvm-svn: 62191

llvm-svn: 62190

llvm-svn: 62185

llvm-svn: 62184

llvm-svn: 62178

scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177

been modified, to avoid trouble in the (unlikely) scenario that
D is a reference to an element in one of those arrays.

llvm-svn: 62173

via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.

llvm-svn: 62169

was not being cleaned by ExpungeNode.

llvm-svn: 62167

llvm-svn: 62166

llvm-svn: 62151

FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block.

llvm-svn: 62144

Use DebugInfo interface to lower dbg_* intrinsics.

llvm-svn: 62127