Commits · 01fa962226d0a3ea022cd339b5104f4669cf031f · Roger Ferrer / llvm-epi-0.8 · GitLab

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Jan 31, 2017
- InterleaveAccessPass: Avoid constructing invalid shuffle masks · 01fa9622
  Matthias Braun authored Jan 31, 2017
  01fa9622
- GlobalISel: merge invoke and call translation paths. · 293f7435
  Tim Northover authored Jan 31, 2017
  293f7435
- MC: Introduce the ABS8 symbol modifier. · d763c4cc
  Peter Collingbourne authored Jan 31, 2017
  d763c4cc
- [X86][XOP] Add test showing failure to combine build vector to vpermil2ps shuffle · 46284517
  Simon Pilgrim authored Jan 31, 2017
  46284517
- Fix a bug in llvm-obdump(1) with the -macho flag disassembling an object · 02d3a378
  Kevin Enderby authored Jan 31, 2017
  02d3a378
- [Instcombine] Combine consecutive identical fences · aec4617d
  Davide Italiano authored Jan 31, 2017
  aec4617d
- Don't combine stores to a swifterror pointer operand to a different type · c368563b
  Arnold Schwaighofer authored Jan 31, 2017
  c368563b
- Explicitly promote indirect calls before sample profile annotation. · 274df5ea
  Dehao Chen authored Jan 31, 2017
  274df5ea
- [InstCombine] add test for possible zext-phi transform; NFC · c0abce81
  Sanjay Patel authored Jan 31, 2017
  c0abce81
- AMDGPU: Use source mods with fcanonicalize · d5d78510
  Matt Arsenault authored Jan 31, 2017
  d5d78510
- [X86] Implement -mfentry · a7c041d1
  Nirav Dave authored Jan 31, 2017
  a7c041d1
- [AMDGPU][mc][tests][NFC] Revert coverage/smoke Gfx7 asm test · e0c3b40d
  Artem Tamazov authored Jan 31, 2017
  e0c3b40d
- AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds · 124f5cc8
  Tom Stellard authored Jan 31, 2017
  124f5cc8
- [X86][SSE] Add support for combining PINSRB into a target shuffle. · 1b39d5db
  Simon Pilgrim authored Jan 31, 2017
  1b39d5db
- [DAGCombine] require UnsafeFPMath for re-association of addition · 8813d5d2
  Nicolai Haehnle authored Jan 31, 2017
  8813d5d2
- [ARM] Avoid using ARM instructions in Thumb mode · 9bf658d5
  Sam Parker authored Jan 31, 2017
  9bf658d5
- [InstCombine] Make sure that LHS and RHS have the same type in · c6d21eba
  Silviu Baranga authored Jan 31, 2017
  c6d21eba
- [X86][SSE] Detect unary PBLEND shuffles. · 4eab18f6
  Simon Pilgrim authored Jan 31, 2017
  4eab18f6
- [X86][SSE] Add support for combining PINSRW into a target shuffle. · c29eab52
  Simon Pilgrim authored Jan 31, 2017
  c29eab52
- [PowerPC][Altivec] Add vmr extended mnemonic · 2f2a6ab9
  Nemanja Ivanovic authored Jan 31, 2017
  2f2a6ab9
- [mips] Addition of the immediate cases for the instructions [d]div, [d]divu · 12850eea
  Simon Dardis authored Jan 31, 2017
  12850eea
- [X86] Add AVX and SSE2 version of MOVSDmr to execution domain fixing table.... · 797e32dd
  Craig Topper authored Jan 31, 2017
  797e32dd
- [AVX-512] Fix copy and paste bug in execution domain fixing tables so that we... · 779e4c5b
  Craig Topper authored Jan 31, 2017
  779e4c5b
- [NVPTX] Implement NVPTXTargetLowering::getSqrtEstimate. · 1c9692a4
  Justin Lebar authored Jan 31, 2017
  1c9692a4
- [X86] Update the broadcast fallback patterns to use shuffle instructions from... · 06e038c6
  Craig Topper authored Jan 31, 2017
  06e038c6
- [X86] Add test cases for AVX1 broadcast fallback patterns when load can't be folded. · 88b0a473
  Craig Topper authored Jan 31, 2017
  88b0a473
- AMDGPU: Generalize matching of v_med3_f32 · f84e5d9a
  Matt Arsenault authored Jan 31, 2017
  f84e5d9a
- InferAddressSpaces: Handle icmp · 72f259b8
  Matt Arsenault authored Jan 31, 2017
  72f259b8
- InferAddressSpaces: Support memory intrinsics · 6d5a8d48
  Matt Arsenault authored Jan 31, 2017
  6d5a8d48
- InferAddressSpaces: Support atomics · 6c907a9b
  Matt Arsenault authored Jan 31, 2017
  6c907a9b
- InferAddressSpaces: Don't replace volatile users · d89a6e11
  Matt Arsenault authored Jan 31, 2017
  d89a6e11
- AMDGPU: Implement hook for InferAddressSpaces · b6491cc8
  Matt Arsenault authored Jan 31, 2017
  b6491cc8
- NVPTX: Move InferAddressSpaces to generic code · 850657a4
  Matt Arsenault authored Jan 31, 2017
  850657a4
- [SCEV] Simplify/generalize howFarToZero solving. · 10d1ff64
  Eli Friedman authored Jan 31, 2017
  10d1ff64
- [ExecutionDepsFix] Improve clearance calculation for loops · 578cf7aa
  Keno Fischer authored Jan 30, 2017
  578cf7aa
- [InstCombine] enable (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2) for vectors with splat constants · 8c5f2361
  Sanjay Patel authored Jan 30, 2017
  8c5f2361
- [WebAssembly] Add wasm support for llvm-readobj · 6d76b7b4
  Derek Schuff authored Jan 30, 2017
  6d76b7b4
- [InstCombine] add vector test for (X <<nsw C1) >>s C2 --> X <<nsw (C1 - C2); NFC · abbb118a
  Sanjay Patel authored Jan 30, 2017
  abbb118a
- NVPTX: Refactor NVPTXInferAddressSpaces to check TTI · 42b64783
  Matt Arsenault authored Jan 30, 2017
  42b64783
- [InstCombine] enable more lshr(shl X, C1), C2 folds for vectors with splat constants · 0c39d56a
  Sanjay Patel authored Jan 30, 2017
  0c39d56a