llvm-svn: 24920

llvm-svn: 24919

bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917

llvm-svn: 24901

llvm-svn: 24900

that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899

llvm-svn: 24898

llvm-svn: 24896

llvm-svn: 24889

  for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888

llvm-svn: 24886

llvm-svn: 24884

Only run lower-allocations and lower-select for the simple isel

llvm-svn: 24881

For example, instead of emitting this:

test:
        save -40112, %o6, %o6   ;; imm too large
        add %i6, -40016, %o0    ;; imm too large
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

emit this:

test:
        sethi 4194264, %g1
        or %g1, 848, %g1
        save %o6, %g1, %o6
        sethi 4194264, %g1
        add %g1, %i6, %g1
        add %i1, 944, %o0
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

which doesn't cause the assembler to barf.

llvm-svn: 24880

llvm-svn: 24879

llvm-svn: 24877

llvm-svn: 24874

us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register.  This also requires some asm printer work
to satisfy the darwin assembler.

For
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

We now produce:
_foo:
        lvx v0, 0, r3
        vaddfp v0, v0, v0
        stvx v0, 0, r3
        blr

Instead of:
_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24872

llvm-svn: 24871

llvm-svn: 24870

llvm-svn: 24867

we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.

llvm-svn: 24859

llvm-svn: 24857

llvm-svn: 24856

llvm-svn: 24855

llvm-svn: 24854

llvm-svn: 24853

llvm-svn: 24852

llvm-svn: 24850

llvm-svn: 24849

llvm-svn: 24848

llvm-svn: 24847

llvm-svn: 24846

llvm-svn: 24845

llvm-svn: 24844

llvm-svn: 24842

llvm-svn: 24841

llvm-svn: 24840

llvm-svn: 24839

llvm-svn: 24838