of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527

vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519

llvm-svn: 137515

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

llvm-svn: 137502

Port over the basic ARM encodings test file to a decoding test file.  Greatly increases our test coverage of basic ARM-mode instructions.

llvm-svn: 137495

llvm-svn: 137486

llvm-svn: 137471

llvm-svn: 137464

MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.

llvm-svn: 137414

is returned through a bitcast.

llvm-svn: 137402

the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.

llvm-svn: 137399

llvm-svn: 137393

llvm-svn: 137389

checked in at r137276 and r137341.

llvm-svn: 137385

SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.

llvm-svn: 137384

warning. 

llvm-svn: 137378

llvm-svn: 137376

llvm-svn: 137372

llvm-svn: 137367

inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362

1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file

llvm-svn: 137361

llvm-svn: 137358

llvm-svn: 137353

llvm-svn: 137347

llvm-svn: 137344

llvm-svn: 137342

llvm-svn: 137340

llvm-svn: 137337

llvm-svn: 137336

llvm-svn: 137335

llvm-svn: 137333

llvm-svn: 137332

llvm-svn: 137331

llvm-svn: 137325

llvm-svn: 137324

llvm-svn: 137323

Correct immediate range for shifter operands.  Patch by James Molloy, with additional encoding fixes added by me.

llvm-svn: 137322

llvm-svn: 137320

Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318

Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316