Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code.

llvm-svn: 142642

llvm-svn: 142630

llvm-svn: 142626

top-down scheduling and top-down scheduling is going away.

llvm-svn: 142621

Separate out ARM MSR instructions into M-class versions and AR-class versions.  This fixes some roundtripping failures.

llvm-svn: 142618

llvm-svn: 142615

AsmParser. This patch adds validation for target data layout strings upon
construction of TargetData objects. An attempt to construct a TargetData object
from a malformed string will trigger an assertion.

llvm-svn: 142605

llvm-svn: 142591

llvm-svn: 142583

llvm-svn: 142581

llvm-svn: 142557

llvm-svn: 142550

Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size.

On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530

llvm-svn: 142485

llvm-svn: 142484

llvm-svn: 142480

llvm-svn: 142460

used with the CMP instruction.

llvm-svn: 142458

This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3.

llvm-svn: 142455

llvm-svn: 142441

register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440

I'll remove/rename the option in a few days.

llvm-svn: 142439

register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437

Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>.

llvm-svn: 142432

instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431

and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429

llvm-svn: 142416

llvm-svn: 142413

llvm-svn: 142412

Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397

llvm-svn: 142395

llvm-svn: 142394

predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390

llvm-svn: 142389

llvm-svn: 142386

llvm-svn: 142381

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

<rdar://problem/10298332>

llvm-svn: 142371

llvm-svn: 142365

llvm-svn: 142363