for specifying fractional bits for fixed point conversions.

llvm-svn: 117501

llvm-svn: 117478

rdar://8477752.

llvm-svn: 117419

llvm-svn: 117418

explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409

llvm-svn: 117188

llvm-svn: 117165

llvm-svn: 117133

llvm-svn: 117121

definitions.

llvm-svn: 117114

llvm-svn: 117108

llvm-svn: 117080

llvm-svn: 117076

llvm-svn: 117072

setup they require. Use this for ARM/Darwin to rematerialize the base
pointer from the frame pointer when required. rdar://8564268

llvm-svn: 116879

llvm-svn: 116768

llvm-svn: 116612

llvm-svn: 116604

llvm-svn: 116588

llvm-svn: 116566

llvm-svn: 116560

llvm-svn: 116537

and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534

pseudonym.

llvm-svn: 116512

llvm-svn: 116498

llvm-svn: 116488

llvm-svn: 116449

llvm-svn: 116447

llvm-svn: 116444

llvm-svn: 116440

llvm-svn: 116437

and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432

llvm-svn: 116428

wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427

llvm-svn: 116421

llvm-svn: 116414

llvm-svn: 116412

arithmetic-with-carry-in instructions.

llvm-svn: 116384

and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377

explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367