- Dec 15, 2010
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Bill Wendling authored
llvm-svn: 121858
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Rafael Espindola authored
With this we don't need the EffectiveSize field anymore. Without that field LayoutFragment only updates offsets and we don't need to invalidate the current fragment when it is relaxed (only the ones following it). This is also a very small improvement in the accuracy of the layout info as we now use the after relaxation size immediately. llvm-svn: 121857
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Rafael Espindola authored
Since we now don't update addresses so early, we might relax a bit more than we need to. This is simillar to the issue in PR8467. llvm-svn: 121856
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Chris Lattner authored
llvm-svn: 121854
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Chris Lattner authored
llvm-svn: 121853
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Rafael Espindola authored
llvm-svn: 121851
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Chris Lattner authored
llvm-svn: 121850
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Chris Lattner authored
llvm-svn: 121849
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Chris Lattner authored
a wider mul if the wider mul is legal. llvm-svn: 121848
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Chris Lattner authored
llvm-svn: 121847
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Chris Lattner authored
result, the top bits are truncated off anyway, just use SRL. llvm-svn: 121846
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Chris Lattner authored
llvm-svn: 121838
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Chris Lattner authored
llvm-svn: 121837
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Bill Wendling authored
llvm-svn: 121832
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Kevin Enderby authored
update the condition codes. These come from my test generator and are just the ones that MC currently assembles correctly. llvm-svn: 121830
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Mikhail Glushenkov authored
llvm-svn: 121829
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Mikhail Glushenkov authored
llvm-svn: 121828
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Mikhail Glushenkov authored
llvm-svn: 121827
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Mikhail Glushenkov authored
llvm-svn: 121826
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Mikhail Glushenkov authored
llvm-svn: 121825
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Mikhail Glushenkov authored
llvm-svn: 121824
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Mikhail Glushenkov authored
llvm-svn: 121823
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Mikhail Glushenkov authored
llvm-svn: 121822
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Bill Wendling authored
llvm-svn: 121820
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Bill Wendling authored
immediate versions. llvm-svn: 121819
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Owen Anderson authored
this case involve a select that simplifies to itself. llvm-svn: 121817
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Owen Anderson authored
llvm-svn: 121816
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Bill Wendling authored
llvm-svn: 121815
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Jim Grosbach authored
llvm-svn: 121812
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Bill Wendling authored
llvm-svn: 121809
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Bill Wendling authored
particular, we want ldr r2, [r3] to be equivalent to ldr r2, [r3, #0] and not ldr r2, [r3, r0] llvm-svn: 121808
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Jakob Stoklund Olesen authored
llvm-svn: 121807
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Jakob Stoklund Olesen authored
llvm-svn: 121806
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Jakob Stoklund Olesen authored
llvm-svn: 121805
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Jakob Stoklund Olesen authored
llvm-svn: 121801
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Jakob Stoklund Olesen authored
registers that alias Reg, including itself. This is almost the same as the existing getAliasSet() method, except for the inclusion of Reg. The name matches the reflexive TRI::regsOverlap(x, y) relation. It is very common to do stuff to a register and all its aliases: stuff(Reg) for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) stuff(*Alias); That can now be written as the simpler: for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) stuff(*Alias); This change requires a bit more constant space for the alias lists because Reg is included and because the empty alias list cannot be shared any longer. If the getAliasSet method is eventually removed, this space can be reclaimed by sharing overlap lists. For instance, %rax and %eax have identical overlap sets. llvm-svn: 121800
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- Dec 14, 2010
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Bill Wendling authored
llvm-svn: 121797
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Bill Wendling authored
is the addition of the FoldableAsLoad & Rematerializable flags to some of the load instructions. ARM has these flags set for them. llvm-svn: 121794
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Evan Cheng authored
regB = move RCX regA = op regB, regC RAX = move regA where both regB and regC are killed. If regB is constrainted to non-compatible physical registers but regC is not constrainted at all, then it's better to commute the instruction. movl %edi, %eax shlq $32, %rcx leaq (%rcx,%rax), %rax => movl %edi, %eax shlq $32, %rcx orq %rcx, %rax rdar://8762995 llvm-svn: 121793
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