Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.

PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766

llvm-svn: 85557

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

llvm-svn: 84652

All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526

llvm-svn: 82390

the MachineInstr ->MCInst lowering process, not in the 
asmprinter.

llvm-svn: 82388

transcode from AT&T to intel syntax with "llvm-mc foo.s -output-asm-variant=1"

llvm-svn: 82385

on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.

llvm-svn: 82263

carry bit) instructions to the Intel instruction
tables.

llvm-svn: 82260

as part string parsing) instructions to the Intel
instruction tables.

llvm-svn: 82089

instructions to the Intel instruction tables.

llvm-svn: 82084

instruction tables.

llvm-svn: 82083

to the Intel instruction tables.

llvm-svn: 82081

frame, to the Intel instruction tables.

llvm-svn: 81995

the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.

llvm-svn: 81994

code in other segments) to the Intel instruction
tables.

llvm-svn: 81953

llvm-svn: 81923

Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914

to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895

versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.

llvm-svn: 81818

for the purposes of the disassembler.

llvm-svn: 81603

operand widths to the Intel instruction tables, for
the purposes of the disassembler.

llvm-svn: 81601

64-bit variants for the disassembler.

llvm-svn: 81591

on rAX and an immediate.

llvm-svn: 81551

various widths.

llvm-svn: 81458

including segment offsets and (for 8-bit operands)
absolute offsets.

llvm-svn: 81457

ones capable of accessing R/M operands instead of just
registers.

llvm-svn: 81456

disabling the use of 16-bit operations on x86. This doesn't yet work for
inline asms with 16-bit constraints, vectors with 16-bit elements,
trampoline code, and perhaps other obscurities, but it's enough to try
some experiments.

llvm-svn: 80930

instruction tables to support segmented addressing (and other objects
of obscure type).
Modified the X86 assembly printers to handle these new operand types.
Added JMP and CALL instructions that use segmented addresses.

llvm-svn: 80857

Added a 64-bit ADD %RAX, imm32 instruction.
Added all 4 forms for AND %rAX, imm and CMP %rAX, imm.

llvm-svn: 80746

Added TEST %rAX, $imm instructions to the Intel tables.  These are required for the X86 disassembler.

llvm-svn: 80696

a register to 0. This fixes PR4814.

llvm-svn: 80445

llvm-svn: 80271

llvm-svn: 80232

moves. This avoids the need to promote the operands (or implicitly
extend them, a partial register update condition), and can reduce
i8 register pressure. This substantially speeds up code such as
write_hex in lib/Support/raw_ostream.cpp.

subclass-coalesce.ll is too trivial and no longer tests what it was
originally intended to test.

llvm-svn: 80184

leads to partial-register definitions. To help avoid redundant
zero-extensions, also teach the h-register matching patterns that
use movzbl to match anyext as well as zext.

llvm-svn: 80099

the register save area if %al is 0. This avoids touching xmm
regsiters when they aren't actually used.

llvm-svn: 79061

llvm-svn: 78733

 - Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.

llvm-svn: 78731