llvm-svn: 198658

This patch adds .abicalls and .set pic0 support which
affects the ELF ABI and its flags. In addition the patch uses
a common interface for both the MipsTargetSteamer and
MipsObjectStreamer that both the integrated and standalone
assemblers will use for the output for these directives.

llvm-svn: 198646

llvm-svn: 198624

The ARM backend has been using most of the MachO related subtarget
checks almost interchangeably, and since the only target it's had to
run on has been IOS (which is all three of MachO, Darwin and IOS) it's
worked out OK so far.

But we'd like to support embedded targets under the "*-*-none-macho"
triple, which means everything starts falling apart and inconsistent
behaviours emerge.

This patch should pick a reasonably sensible set of behaviours for the
new triple (and any others that come along, with luck). Some choices
were debatable (notably FP == r7 or r11), but we can revisit those
later when deficiencies become apparent.

llvm-svn: 198617

llvm-svn: 198616

llvm-svn: 198615

This requires a knowledge of the stack size which is not known until
the frame is complete, hence the need for the XCoreFTAOElim pass
which lowers the XCoreISD::FRAME_TO_ARGS_OFFSET instrution into its
final form.

llvm-svn: 198614

Only handles a depth of zero (the same as FRAMEADDR)

llvm-svn: 198613

llvm-svn: 198612

We also narrow the liveness of FP & LR during the prologue to
reflect the actual usage of the registers.
I have been unable to construct a test to prove the previous live
range was too large.

llvm-svn: 198611

This common functionality will be used to lower FRAME_TO_ARGS_OFFSET.

llvm-svn: 198610

llvm-svn: 198609

Longer term, we want to move users to "*-*-*-macho" for embedded work, but for
now people are relying on the last thing we told them, which is unfortunately
"*-*-darwin-eabi".

rdar://problem/15703934

llvm-svn: 198602

llvm-svn: 198593

llvm-svn: 198592

llvm-svn: 198591

llvm-svn: 198588

llvm-svn: 198587

The 0x66 prefix toggles between 16-bit and 32-bit addressing mode.
So in 32-bit mode it is used to switch to 16-bit addressing mode for the
following instruction, while in 16-bit mode it's the other way round — it's
used to switch to 32-bit mode instead.

Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode,
and introduce a new OpSize16 bit which is used in 16-bit mode instead.

This is just the basic infrastructure for that change; a subsequent patch
will add the new OpSize16 bit to the 32-bit instructions that need it.

Patch from David Woodhouse.

llvm-svn: 198586

llvm-svn: 198585

This is not really expected to work right yet. Mostly because we will
still emit the OpSize (0x66) prefix in all the wrong places, along with
a number of other corner cases. Those will all be fixed in the subsequent
commits.

Patch from David Woodhouse.

llvm-svn: 198584

llvm-svn: 198580

This moves the check up into the parent class so that all targets can use it
without having to copy (and keep in sync) the same error message.

llvm-svn: 198579

Move the ARM EHABI unwind opcode definitions from the ARM MCTargetDesc into LLVM
Support.  This enables sharing of the definitions across the ARM target code as
well as llvm-readobj.  This will allow implementation of the unwind decoding in
llvm-readobj.

llvm-svn: 198576

llvm-svn: 198567

Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.

llvm-svn: 198566

Remove opcode from MOV32r0 that I accidentally left when I converted it to Pseudo. Remove FIXME as well.

llvm-svn: 198564

Fix indentation, name registers similar to ARM ARM.

No functionality change!

llvm-svn: 198563

AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD;
Optimized a truncate pattern.

llvm-svn: 198562

Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557

llvm-svn: 198551

llvm-svn: 198550

llvm-svn: 198547

Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.

llvm-svn: 198545

Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack.

llvm-svn: 198544

Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions.

llvm-svn: 198543

llvm-svn: 198533

__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

llvm-svn: 198531

Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.

llvm-svn: 198530

Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack.

llvm-svn: 198515