- Rename TargetRegisterDesc to MCRegisterDesc.

llvm-svn: 133820

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

llvm-svn: 133759

llvm-svn: 133739

llvm-svn: 133726

llvm-svn: 133679

to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.

llvm-svn: 133565

This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

llvm-svn: 133524

movd when assembling.

llvm-svn: 133452

llvm-svn: 133347

llvm-svn: 133325

llvm-svn: 133308

considered safe enough in this context.

llvm-svn: 133159

Original patch by Syoyo Fujita with more comments by me.

llvm-svn: 133153

This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

llvm-svn: 133105

optimizations when emitting calls to the function;  instead those calls may
use faster relocations which require the function to be immediately resolved
upon loading the dynamic object featuring the call.  This is useful when it
is known that the function will be called frequently and pervasively and
therefore there is no merit in delaying binding of the function.

Currently only implemented for x86-64, where it turns into a call through
the global offset table.

Patch by Dan Gohman, who assures me that he's going to add LangRef documentation
for this once it's committed.

llvm-svn: 133080

or instruction cache access. Update the targets to match it and also teach
autoupgrade.

llvm-svn: 132976

llvm-svn: 132964

we try to branch to them.

Before we were creating successor lists with duplicated entries. Fixing that
found a bug in isBlockOnlyReachableByFallthrough that would causes it to
return the wrong answer for

-----------
...
jne foo
jmp bar

foo:
----------

llvm-svn: 132882

functionality change.

Later on, we'll use the flag to emit SEH pseudo-ops that describe how the
call frame was built.

llvm-svn: 132880

memcpy/memset symbol doesn't get marked up correctly in PIC modes otherwise.
Should fix llvm-x86_64-linux-checks buildbot.  Followup to r132864.

llvm-svn: 132869

rdar://9431466

llvm-svn: 132864

PR10092 (second try): Don't crash on a load without a momoperand; fast-isel creates loads like this.

llvm-svn: 132826

Chris fixed this README a while back by changing how clang generates code for structs like the given struct.

llvm-svn: 132815

llvm-svn: 132795

Add a check to make sure we don't crash with strange configurations where we do fast-isel, then try to fold instructions. PR10092.

llvm-svn: 132789

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

llvm-svn: 132781

No functional change.

Part of PR6965

llvm-svn: 132763

load.  rdar://problem/6373334

llvm-svn: 132696

rdar://problem/5993888

llvm-svn: 132606

Part of rdar://9119939

llvm-svn: 132510

allocation orders.

llvm-svn: 132509

llvm-svn: 132479

rdar://problem/6373334

llvm-svn: 132458

No functional change.

llvm-svn: 132455

llvm-svn: 132451

llvm-svn: 132424

llvm-svn: 132419

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398