llvm-svn: 85410

llvm-svn: 85362

llvm-svn: 85186

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

llvm-svn: 82788

llvm-svn: 82483

llvm-svn: 78604

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

llvm-svn: 78101

llvm-svn: 78085

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 76390

llvm-svn: 75254

llvm-svn: 73252

llvm-svn: 60901

llvm-svn: 60487

llvm-svn: 59344

llvm-svn: 59234

llvm-svn: 59107

llvm-svn: 59104

llvm-svn: 59102

llvm-svn: 59088

llvm-svn: 59084

llvm-svn: 59074

llvm-svn: 59016

llvm-svn: 58800

llvm-svn: 56126

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017

llvm-svn: 45821

llvm-svn: 45727

llvm-svn: 45667

llvm-svn: 45656

llvm-svn: 45653

llvm-svn: 45418

Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.

llvm-svn: 44960

llvm-svn: 41863

llvm-svn: 40887

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033