allocas.

llvm-svn: 156458

llvm-svn: 156457

llvm-svn: 156456

llvm-svn: 156441

llvm-svn: 156416

llvm-svn: 156411

Patch by Reed Kotler.

llvm-svn: 156408

Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.

Patch by Yiannis Tsiouris!

llvm-svn: 156382

llvm-svn: 156375

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

Test cases for this code are coming. It is not used for anything yet.

llvm-svn: 156327

This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

llvm-svn: 156317

single use.
rdar://11360370

llvm-svn: 156316

This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709
llvm-svn: 156312

Patch by Jack Carter.

llvm-svn: 156295

Patch by Jack Carter.

llvm-svn: 156294

Patch by Jack Carter.

llvm-svn: 156293

Patch by Jack Carter.

llvm-svn: 156292

llvm-svn: 156287

Patch by Jack Carter.

llvm-svn: 156285

Patch by Jack Carter.

llvm-svn: 156284

Patch by Jack Carter.

llvm-svn: 156283

llvm-svn: 156282

llvm-svn: 156281

Patch by Jack Carter.

llvm-svn: 156280

from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279

Patch by Jack Carter.

llvm-svn: 156278

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277

Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions.

llvm-svn: 156268

Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes.

llvm-svn: 156266

llvm-svn: 156265

llvm-svn: 156241

This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

llvm-svn: 156233

llvm-svn: 156232

llvm-svn: 156226

This fixes a couple of Clang warnings in release builds of LLVM:

* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp

llvm-svn: 156216

SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .

llvm-svn: 156213

where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046

llvm-svn: 156212

In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
  default: assert(0 && "Unknown condition code");
  ^
1 warning generated.

The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.

llvm-svn: 156209

This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.

The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

llvm-svn: 156196