llvm-svn: 150436

The scheduler will sometimes check the implicit-def list on instructions
to properly handle pre-colored DAG edges.

Also check any register mask operands for physreg clobbers.

llvm-svn: 150428

llvm-svn: 150411

llvm-svn: 150404

Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.

llvm-svn: 150383

This patch addresses the problem of poor code generation for the zext
v8i8 -> v8i32 on AVX machines. The codegen often scalarizes ANY_EXTEND nodes.
The DAGCombiner has two optimizations that can mitigate the problem. First,
if all of the operands of a BUILD_VECTOR node are extracted from an ZEXT/ANYEXT
nodes, then it is possible to create a new simplified BUILD_VECTOR which uses
UNDEFS/ZERO values to eliminate the scalar ZEXT/ANYEXT nodes.
Second, another dag combine optimization lowers BUILD_VECTOR into a shuffle
vector instruction.

In the case of zext v8i8->v8i32 on AVX, a value in an XMM register is to be
shuffled into a wide YMM register.

This patch modifes the second optimization and allows the creation of
shuffle vectors even when the newly generated vector and the original vector
from which we extract the values are of different types.

llvm-svn: 150340

Patch by Kai Nacke!

llvm-svn: 150307

In case the MachineScheduling pass I'm working on doesn't work well
for another target, they can completely override it. This also adds a
hook immediately after the RegAlloc pass to cleanup immediately after
vregs go away. We may want to fold it into the postRA hook later.

llvm-svn: 150298

When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

llvm-svn: 150288

Again the goal is to produce identical assembly with register mask
operands enabled.

llvm-svn: 150287

llvm-svn: 150286

It can be necessary to detach a register mask pointer from its
MachineOperand. This method is convenient for checking clobbered
physregs on a detached bitmask pointer.

llvm-svn: 150261

This makes global live range splitting behave identically with and
without register mask operands.

This is not necessarily the best way of using register masks for live
range splitting.  It would be more efficient to first split global live
ranges around calls (i.e., register masks), and reserve the fine grained
per-physreg interference guidance for global live ranges that do not
cross calls.

For now the goal is to produce identical assembly when enabling register
masks.

llvm-svn: 150259

llvm-svn: 150258

Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.

Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245

llvm-svn: 150233

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

llvm-svn: 150225

llvm-svn: 150224

When checking a local live range for interference, restrict the binary
search to the single block.

llvm-svn: 150220

Provide API to get a list of register mask slots and bits in a basic
block.

llvm-svn: 150219

No looping and binary searches necessary.

Return a pointer to the containing block instead of just a bool.

llvm-svn: 150218

llvm-svn: 150214

This only adds the interference checks required for correctness.
We still need to take advantage of register masks for the
interference driven live range splitting.

llvm-svn: 150191

Failure to preserve kills was causing LiveIntervals to miss some EFLAGS live
ranges. Unfortunately I've been unable to reduce a good test case yet.

llvm-svn: 150152

llvm-svn: 150150

llvm-svn: 150149

Split CodeGen into stages.
Distinguish between optimization and correctness.

llvm-svn: 150122

llvm-svn: 150121

This does make a difference, at least when using RABasic.

llvm-svn: 150118

I think this was already the intention, but DeadMachineInstructionElim
was accidentally tracking the liveness of reserved registers. Now,
instructions with reserved defs are never deleted.

This prevents the call stack adjustment instructions from getting
deleted when enabling register masks.

llvm-svn: 150116

For simplicity, treat calls with register masks as basic block
boundaries.  This means we can't copy propagate callee-saved registers
across calls, but I don't think that is a big deal.

llvm-svn: 150108

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

llvm-svn: 150100

llvm-svn: 150099

llvm-svn: 150098

llvm-svn: 150097

llvm-svn: 150096

llvm-svn: 150095

llvm-svn: 150094

llvm-svn: 150093