llvm-svn: 126671

only existed as the result of a misunderstanding.

llvm-svn: 126669

was started for in the foreseeable future.

llvm-svn: 126668

[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
      and 256-bit forms.  Because the number of elements in a vector
      does not determine the vector type (4 elements could be v4f32 or
      v4f64), pass the full type of the vector to decode routines.

llvm-svn: 126664

needed two predicate operands before the imm operand.

llvm-svn: 126662

llvm-svn: 126661

patch to the front-end.  Radar 7662569.

llvm-svn: 126655

The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.

llvm-svn: 126651

Based on a patch by Alistair Lynn.

llvm-svn: 126647

llvm-svn: 126645

also have a zero when numerator = denominator. Reverts parts of r126635 and
r126637.

llvm-svn: 126644

PR9343.

llvm-svn: 126643

llvm-svn: 126642

srem instruction.

llvm-svn: 126637

- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636

argument), regardless of the divisor. Teach instcombine about this and fix
test7 in PR9343!

llvm-svn: 126635

llvm-svn: 126578

llvm-svn: 126574

Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.

It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568

llvm-svn: 126565

llvm-svn: 126564

This follows the interface of getNodeAttributes.

llvm-svn: 126562

llvm-svn: 126558

Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.

1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557

llvm-svn: 126526

llvm-svn: 126518

llvm-svn: 126488

Yes, there are other types than i8* and GEPs on them can produce an add+multiply.
We don't consider that cheap enough to be speculatively executed.

llvm-svn: 126481

llvm-svn: 126477

llvm-svn: 126471

llvm-svn: 126467

is possible to do better if the high bit is set in either KnownZero/KnownOne, but
in practice NumSignBits is always 1 when we are zero extending because nothing
is known about that register.

llvm-svn: 126465

actually larger.

llvm-svn: 126464

llvm-svn: 126463

D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312

llvm-svn: 126457

llvm-svn: 126452

New live ranges are assigned in long -> short order, but live ranges that have
been evicted at least once are deferred and assigned in short -> long order.

Also disable splitting and spilling for live ranges seen for the first time.

The intention is to create a realistic interference pattern from the heavy live
ranges before starting splitting and spilling around it.

llvm-svn: 126451

llvm-svn: 126450

llvm-svn: 126445

Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.

llvm-svn: 126443