llvm-svn: 52923

it impossible to create a MERGE_VALUES node with
only one result: sometimes it is useful to be able
to create a node with only one result out of one of
the results of a node with more than one result, for
example because the new node will eventually be used
to replace a one-result node using ReplaceAllUsesWith,
cf X86TargetLowering::ExpandFP_TO_SINT.  On the other
hand, most users of MERGE_VALUES don't need this and
for them the optimization was valuable.  So add a new
utility method getMergeValues for creating MERGE_VALUES
nodes which by default performs the optimization.
Change almost everywhere to use getMergeValues (and
tidy some stuff up at the same time).

llvm-svn: 52893

llvm-svn: 52613

of apint codegen failure is the DAG combiner doing
the wrong thing because it was comparing MVT's using
< rather than comparing the number of bits.  Removing
the < method makes this mistake impossible to commit.
Instead, add helper methods for comparing bits and use
them.

llvm-svn: 52098

and better control the abstraction.  Rename the type
to MVT.  To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits().  Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).

llvm-svn: 52044

issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.

llvm-svn: 51884

function to flush a specified std::ostream.

llvm-svn: 51705

are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both.  The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.

llvm-svn: 51118

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().

llvm-svn: 50462

the default impl.

llvm-svn: 50311

on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.

llvm-svn: 49572

llvm-svn: 48995

llvm-svn: 48801

Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.

llvm-svn: 48575

that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256

- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.

llvm-svn: 48197

llvm-svn: 48169

llvm-svn: 48152

return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.

llvm-svn: 48145

cell really does support cross-regclass moves, because R3 is in lots of different regclasses, and the code is not consistent when it comes to value tracking.

llvm-svn: 48119

Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.

llvm-svn: 48042

upper and lower 32-bits are the same (in addition to 0 and -1 previously.)

llvm-svn: 47985

  using IL, ILA, et. al. v2i64 and i64 are now supported by
  the select bits (SELB) instruction.

- Add missing comparison operations (testcase forthcoming)

- More multiclass refactoring.

llvm-svn: 47973

llvm-svn: 47703

would have been a Godsend here!

llvm-svn: 47625

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47375

I cannot find a libgcc function for this builtin.  Therefor expanding it to a noop (which is how it use to be treated).  If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.

llvm-svn: 47213

it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to.  Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.

llvm-svn: 47143

which allows us to kill a target-specific node.

llvm-svn: 47127

llvm-svn: 47115

to pass the mask APInt by value, not by reference. 

llvm-svn: 47096

DAGCombine is now quite good at zapifying them.

llvm-svn: 47053

Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.

llvm-svn: 47039

llvm-svn: 46930

It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.

llvm-svn: 46893

Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is consistent with the definition in td file.

llvm-svn: 46775

Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.

llvm-svn: 46724