reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.

llvm-svn: 95951

with "tied memory operands", which is wrong.

llvm-svn: 95950

llvm-svn: 95949

movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

Kees van Reeuwijk!

llvm-svn: 95946

implement support for it) that the stack should be forcibly realigned in the
prologue (and the process reversed in the epilogue).

llvm-svn: 95945

This time with fixed test cases.

llvm-svn: 95938

	testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935

implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.

llvm-svn: 95929

8 or 32-bit immediates, which allows the new encoder to handle
them.

llvm-svn: 95927

llvm-svn: 95926

llvm-svn: 95925

the tables to be const.  Teach MCCodeEmitter to handle
the target-indep kinds so that we don't crash on them.

llvm-svn: 95924

llvm-svn: 95921

llvm-svn: 95920

llvm-svn: 95918

Also avoid division by zero.

llvm-svn: 95917

llvm-svn: 95916

llvm-svn: 95915

llvm-svn: 95903

use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901

Sorry!

llvm-svn: 95892

same dead instruction.

llvm-svn: 95890

llvm-svn: 95889

A8.6.297

llvm-svn: 95885

llvm-svn: 95884

Use SmallVector instead of std::vector for better speed when indirectbr has
few successors.

llvm-svn: 95879

symbols.

Thanks to Duncan Sands for the testcase!

llvm-svn: 95877

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

llvm-svn: 95871

fixes the remaining x86-64 jit failures afaik.

llvm-svn: 95867

r12b, etc) also encodes to a R/M value of 4, which is just
as illegal as ESP/RSP for the non-sib version an address.

This fixes x86-64 jit miscompilations of a bunch of programs.

llvm-svn: 95866

Stub out some dummy fixups to make things work.

We can now emit fixups like this:
	subl	$20, %esp               ## encoding: [0x83,0xec,A]
                                        ##   fixup A - offset: 2, value: 20, kind: fixup_1byte_imm

Emitting $20 as a single-byte fixup to be later resolved
by the assembler is ridiculous of course (vs just emitting
the byte) but this is a failure of the matcher, which 
should be producing an imm of 20, not an MCExpr of 20.

llvm-svn: 95860

and rename it to EmitImmediate.

llvm-svn: 95859

llvm-svn: 95858

llvm-svn: 95857

llvm-svn: 95856

what it does.  Enhance it to return false to optimizing vector
sign extensions from vector comparisions, which is the idiom used
to get a splatted vector for a vector comparison.

Doing this breaks vector-casts.ll, add some compensating 
transformations to handle the important case they cover without
depending on this canonicalization.

This fixes rdar://7434900 a serious pessimization of vector compares.

llvm-svn: 95855

block.  Other blocks may have pointer cycles that will crash
basicaa and other alias analyses.  In any case, there is no
point wasting cycles optimizing dead blocks.  This fixes 
rdar://7635088

llvm-svn: 95852