llvm-svn: 136409

llvm-svn: 136408

Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406

llvm-svn: 136405

'atomicrmw' instructions, which allow representing all the current atomic
rmw intrinsics.

The allowed operands for these instructions are heavily restricted at the
moment; we can probably loosen it a bit, but supporting general
first-class types (where it makes sense) might get a bit complicated,
given how SelectionDAG works.

As an initial cut, these operations do not support specifying an alignment,
but it would be possible to add if we think it's useful. Specifying an
alignment lower than the natural alignment would be essentially
impossible to support on anything other than x86, but specifying a greater
alignment would be possible.  I can't think of any useful optimizations which
would use that information, but maybe someone else has ideas.

Optimizer/codegen support coming soon.

llvm-svn: 136404

llvm-svn: 136403

llvm-svn: 136402

Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401

llvm-svn: 136400

Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399

there is no frequency difference whether condition is in the header or in
the latch.

llvm-svn: 136398

llvm-svn: 136396

consistently in the ASTReader.

llvm-svn: 136395

by specifying your EXE make variable via your Makefile or within the Python test script.

llvm-svn: 136394

llvm-svn: 136392

IDs properly, although the mapping itself is still trivial.

llvm-svn: 136391

llvm-svn: 136390

llvm-svn: 136389

There are two conflicting strategies in play:

- Under high register pressure, we want to assign large live ranges
  first. Smaller live ranges are easier to place afterwards.

- Live range splitting is guided by interference, so splitting should be
  deferred until interference is as realistic as possible.

With the recent changes to the live range stages, and with compact
regions enabled, it is less traumatic to split a live range too early.
If some of the split products were too big, they can often be split
again.

By reversing the RS_Split order, we get this queue order:

1. Normal live ranges, large to small.
2. RS_Split live ranges, large to small.

The large-to-small order improves RAGreedy's puzzle solving skills under
high register pressure. It may cause a bit more iterated splitting, but
we handle that better now.

With this change, -compact-regions is mostly an improvement on SPEC.

llvm-svn: 136388

This should be the only code necessary for DWARF EH prepare.

llvm-svn: 136387

rdar://problem/9691614.

llvm-svn: 136386

Fix a test case that was intermittently failing.  The issue was that instantiations are not stored in an order preserving structure, so the print order may be impacted.  Modified test case to do two FileCheck passes to ensure that both instantiations are in the same place.

Test originially commited at r136306 and temporarily silenced at r136348.

llvm-svn: 136385

llvm-svn: 136384

analysis. This includes checking that the attributes are applied in the
correct contexts and with the correct number of arguments.

llvm-svn: 136383

llvm-svn: 136381

llvm-svn: 136380

llvm-svn: 136379

point, ASTReader::InitializeSema() has very little interesting work,
*except* issues stemming from preloaded declarations. That's something
we'll still need to cope with.

llvm-svn: 136378

llvm-svn: 136377

Refactor the */& mismatch fixit generation out of SemaOverload and provide a simple conversion checking function.

llvm-svn: 136376

llvm-svn: 136375

Module member to being an ASTReader member; we want it to be
centralized for lazy deserialization.

llvm-svn: 136373

completely broken deserialization mapping code we had for VTableUses,
which would have broken horribly as soon as our local-to-global ID
mapping became interesting.

llvm-svn: 136371

llvm-svn: 136370

llvm-svn: 136369

llvm-svn: 136368

llvm-svn: 136367

llvm-svn: 136366

llvm-svn: 136365

scoped_lockable, and no_thread_safety_analysis attributes, all for thread safety analysis

llvm-svn: 136364