Commits · 0a109000705afd3dacbc1ddec29081d81ca55bae · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Sep 25, 2015
- AMDGPU: Disable some passes that are not meaningful · 0a109000
  Matt Arsenault authored Sep 25, 2015
  0a109000
- AMDGPU: Handle i64->v2i32 loads/stores in PreprocessISelDAG · 4bf43d4e
  Matt Arsenault authored Sep 25, 2015
  4bf43d4e
- AMDGPU: Fix recomputing dominator tree unnecessarily · 0cb8517d
  Matt Arsenault authored Sep 25, 2015
  0cb8517d
- AMDGPU: Re-justify workaround and fix worked around problem · 2d6fdb84
  Matt Arsenault authored Sep 25, 2015
  2d6fdb84
- AMDGPU: Don't create REG_SEQUENCE with SGPR dest and VGPR sources · 3ad55ec9
  Matt Arsenault authored Sep 25, 2015
  3ad55ec9
- AMDGPU: Fix not adding exec to defs of cmpx instruction pseudos · 6525aa35
  Matt Arsenault authored Sep 25, 2015
  6525aa35
- AMDGPU: Improve accuracy of instruction rates for VOPC · 5f70436c
  Matt Arsenault authored Sep 25, 2015
  5f70436c
- ARM: make -Asserts,-Werror=unused-variable build happy · 8e99f507
  Saleem Abdulrasool authored Sep 25, 2015
  8e99f507
- ARM: address WoA division limitation · fe83b502
  Saleem Abdulrasool authored Sep 25, 2015
  fe83b502
- AMDGPU: Remove unused includes · 8aa99736
  Matt Arsenault authored Sep 25, 2015
  8aa99736
Sep 24, 2015
- [AArch64] Improve the readability of the ld/st optimization pass. NFC. · b02f5a5a
  Chad Rosier authored Sep 24, 2015
  b02f5a5a
- [X86][SSE2] Fix zero/any extension shuffles that don't start from the first element · 68d0050c
  Simon Pilgrim authored Sep 24, 2015
  68d0050c
- AMDGPU: Add s_dcache_* instructions · e66621b3
  Matt Arsenault authored Sep 24, 2015
  e66621b3
- AMDGPU: Add cache invalidation instructions. · d6adfb40
  Matt Arsenault authored Sep 24, 2015
  d6adfb40
- [AArch64] The paired post-increment store instruction has an output register. · 7cd472b7
  Chad Rosier authored Sep 24, 2015
  7cd472b7
- [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def · cf296444
  Artyom Skrobov authored Sep 24, 2015
  cf296444
- [mips] Use PredicateControl for the MSA ASE instructions. NFC. · 090f6e41
  Daniel Sanders authored Sep 24, 2015
  090f6e41
- Introduce target hook for optimizing register copies · 68d93864
  Matt Arsenault authored Sep 24, 2015
  68d93864
- AMDGPU: Return after instruction is processed. · e068f9a2
  Matt Arsenault authored Sep 24, 2015
  e068f9a2
- AMDGPU: Remove another unnecessary check from commuteInstruction · 708586fa
  Matt Arsenault authored Sep 24, 2015
  708586fa
- AMDGPU: Add readonly to InstrMapping functions · fa242960
  Matt Arsenault authored Sep 24, 2015
  fa242960
- AMDGPU: Fix printing trailing whitespace for mubuf atomics · cab64f1c
  Matt Arsenault authored Sep 24, 2015
  cab64f1c
- AMDGPU: Reduce number of copies emitted · c8e2ce40
  Matt Arsenault authored Sep 24, 2015
  c8e2ce40
- ARM: fix folding stack adjustment (again again again...) · beb5bccf
  Tim Northover authored Sep 23, 2015
  beb5bccf
Sep 23, 2015
- [x86] replace integer 'xor' ops with packed SSE FP 'xor' ops when operating on FP scalars · 1a653466
  Sanjay Patel authored Sep 23, 2015
  1a653466
- [x86] replace integer 'or' ops with packed SSE FP 'or' ops when operating on FP scalars · aba37553
  Sanjay Patel authored Sep 23, 2015
  aba37553
- Android support for SafeStack. · a2002b08
  Evgeniy Stepanov authored Sep 23, 2015
  a2002b08
- move call to convertIntLogicToFPLogic up; NFCI · b14ecd34
  Sanjay Patel authored Sep 23, 2015
  b14ecd34
- [x86] move code for converting int logic to FP logic to a helper function; NFCI · ade3abd2
  Sanjay Patel authored Sep 23, 2015
  ade3abd2
- [x86] replace integer 'and' ops with packed SSE FP 'and' ops when operating on FP scalars · df2495f3
  Sanjay Patel authored Sep 23, 2015
  df2495f3
- [WebAssembly] Fix hasAddr64 being used before being initializer. · 979840d3
  Dan Gohman authored Sep 23, 2015
  979840d3
- Fix CodeGen/WebAssembly/global.ll test under ASAN. · a3eaa204
  Alexander Kornienko authored Sep 23, 2015
  a3eaa204
- [AArch64] Refactor pre- and post-index merge fuctions into a single function. NFC. · 2dfd3549
  Chad Rosier authored Sep 23, 2015
  2dfd3549
- [ARM] Add option to force fast-isel · f2ed5c68
  Oliver Stannard authored Sep 23, 2015
  f2ed5c68
- [X86][SSE] Replace 128-bit SSE41 PMOVSX intrinsics with native IR · 9cb018b6
  Simon Pilgrim authored Sep 23, 2015
  9cb018b6
- [SCEV] Introduce ScalarEvolution::getOne and getZero. · 2aacc0ec
  Sanjoy Das authored Sep 23, 2015
  2aacc0ec
- Revert "Android support for SafeStack." · 8d0e3011
  Evgeniy Stepanov authored Sep 23, 2015
  8d0e3011
- Android support for SafeStack. · ce2e16f0
  Evgeniy Stepanov authored Sep 23, 2015
  ce2e16f0
Sep 22, 2015
- [ARM] Emit clrex in the expanded cmpxchg fail block. · 81616a72
  Ahmed Bougacha authored Sep 22, 2015
  81616a72
- [AArch64] Emit clrex in the expanded cmpxchg fail block. · 07a844d7
  Ahmed Bougacha authored Sep 22, 2015
  07a844d7