LiveInterval, etc to raw_ostream.

llvm-svn: 76965

- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381

Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.

llvm-svn: 73346

llvm-svn: 70821

In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However,  reloads and restores might be folded into uses / defs and freed registers might not be used at all.

VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.

Not yet enabled. This is part 1. More coming.

llvm-svn: 70787

llvm-svn: 68099

llvm-svn: 68092

llvm-svn: 67000

llvm-svn: 66870

Reorganization: Move the Spiller out of VirtRegMap.cpp into its own files.  No (intended) functionality change.

llvm-svn: 66720

Yet another case where the spiller marked two uses of the same register on the same instruction as kill. This fixes PR3706.

llvm-svn: 66428

llvm-svn: 66363

llvm-svn: 65679

llvm-svn: 65498

If an available register falls through to a succ block, unset the last kill. Sorry, it's impossible to reduce a sensible test case. It basically requires the moon and stars to align in order to cause a failure.

llvm-svn: 65497

A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.

llvm-svn: 64745

llvm-svn: 64428

the new way, where all of the information is passed on SDNodes and machine
instructions.

llvm-svn: 64427

llvm-svn: 64381

It's (currently) not safe to keep certain physical registers live across basic blocks, e.g. x86 fp stack registers.

llvm-svn: 64374

If availability info is kept when fallthrough into a bb, add the available registers to live-in set.

llvm-svn: 64372

Remove a bogus assertion. It's possible a live-in available value is used by a previous instruction.

llvm-svn: 64339

Implement PR3495: local spiller optimization. The local spiller can now keep availability information over BB boundaries. It visits BB's in depth first order. After visiting a BB if it find a successor which has a single predecessor it visits the successor next without clearing the availability information. This allows the successor to omit reloads or change them into copies.

llvm-svn: 64298

llvm-svn: 63599

llvm-svn: 62600

llvm-svn: 60392

Patch by Lang Hames!

llvm-svn: 57720

llvm-svn: 57673

instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.

llvm-svn: 57521

ENABLE_EXPENSIVE_CHECKS for finding this.

llvm-svn: 57181

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 56085

llvm-svn: 56065

Fix an overly strict assertion. Source register of a copy may not be killed, it may be killed by an implicit super-register use.

llvm-svn: 55762

llvm-svn: 54968

llvm-svn: 54375

llvm-svn: 53766

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

llvm-svn: 52450

llvm-svn: 52309