purely mechanical.

llvm-svn: 23778

redundant after the change.

llvm-svn: 23759

SelectIntImmediateExpr dead.

llvm-svn: 23753

llvm-svn: 23752

llvm-svn: 23751

llvm-svn: 23750

llvm-svn: 23749

llvm-svn: 23746

This completes the grand PPC file renaming

llvm-svn: 23745

and PPC32JITInfo classes should be merged.

llvm-svn: 23744

llvm-svn: 23743

llvm-svn: 23742

still should be merged into the PPC32TargetMachine class

llvm-svn: 23741

llvm-svn: 23740

llvm-svn: 23739

llvm-svn: 23738

llvm-svn: 23737

from the .td file that correspond to it

llvm-svn: 23736

We will decide with subtarget support whether we ever use an i64 register
class.

llvm-svn: 23734

llvm-svn: 23731

llvm-svn: 23727

llvm-svn: 23681

the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.

llvm-svn: 23670

merge, and using subtarget info for ptr size.

llvm-svn: 23668

llvm-svn: 23666

is faster and uses less stack space.  This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel

llvm-svn: 23664

classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll

llvm-svn: 23654

llvm-svn: 23650

llvm-svn: 23649

llvm-svn: 23648

helps but not enough.

Start pulling cases out of PPC32DAGToDAGISel::Select.  With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes).  Pulling this first function out gets us down to 8224.  More
to come :(

llvm-svn: 23647

for globals

llvm-svn: 23608

llvm-svn: 23592

the comparison to be 64-bits.  This is fine because extensions from float
to double are free.

llvm-svn: 23589

split the FSEL family into 4 things instead of just two.

llvm-svn: 23588

llvm-svn: 23587

we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch.  For example, emit this:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        ble cr0, LBBl29_z__44
        b LBBl29_z__48                   *** NOT PART OF LOOP

Instead of:

LBBl29_z__44:
        stw r9, 0(r15)
        stw r9, 4(r15)
        stw r9, 8(r15)
        stw r9, 12(r15)
        addi r15, r15, 16
        addi r8, r8, 1
        cmpw cr0, r8, r28
        bgt cr0, LBBl29_z__48            *** PART OF LOOP!
        b LBBl29_z__44

The former sequence has one fewer dispatch group for the loop body.

llvm-svn: 23582

llvm-svn: 23581

llvm-svn: 23578

These are used to represent float and double values, and the two regclasses
contain the same physical registers.

llvm-svn: 23577