- Jul 14, 2011
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Eric Christopher authored
when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
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Jim Grosbach authored
Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
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Bruno Cardoso Lopes authored
llvm-svn: 135171
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Benjamin Kramer authored
llvm-svn: 135169
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Jim Grosbach authored
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
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Jim Grosbach authored
The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
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Richard Osborne authored
instructions. llvm-svn: 135146
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Nadav Rotem authored
[VECTOR-SELECT] During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
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Evan Cheng authored
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are other cases of violations, but this is probably the worst. This patch is but one small step towards fixing this. 500 more steps to go. :-( llvm-svn: 135131
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Benjamin Kramer authored
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. llvm-svn: 135126
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Eli Friedman authored
Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. llvm-svn: 135120
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Jim Grosbach authored
Add instalias for default 'sy' option. Add tests. llvm-svn: 135116
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Jim Grosbach authored
llvm-svn: 135112
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Jim Grosbach authored
Flesh out the options supported for the instruction. Shuffle tests a bit and add entries for the rest of the options. Add an alias to handle the default operand of "sy". llvm-svn: 135109
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Jim Grosbach authored
llvm-svn: 135107
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Owen Anderson authored
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. llvm-svn: 135106
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Bill Wendling authored
The frameless unwind stack has a special encoding, the algorithm for which is in "permuteEncode". llvm-svn: 135103
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Jim Grosbach authored
Add range checking and testing for parsing and encoding of DBG instruction. llvm-svn: 135102
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Jim Grosbach authored
llvm-svn: 135094
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Jim Grosbach authored
llvm-svn: 135093
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Jim Grosbach authored
llvm-svn: 135092
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- Jul 13, 2011
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Bruno Cardoso Lopes authored
general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
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Bruno Cardoso Lopes authored
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN instruction. Rename it. llvm-svn: 135087
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Jim Grosbach authored
Combine redundant base classes and such. No indended functional change. llvm-svn: 135085
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Eli Friedman authored
Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. <rdar://problem/9763308> llvm-svn: 135084
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Jim Grosbach authored
llvm-svn: 135082
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Jim Grosbach authored
They're all Thumb2 only, not just some of them. More refactoring cleanup coming. llvm-svn: 135081
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Eli Friedman authored
Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress. Part of <rdar://problem/9763308>. llvm-svn: 135079
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Jim Grosbach authored
llvm-svn: 135077
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Jim Grosbach authored
llvm-svn: 135076
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Jim Grosbach authored
llvm-svn: 135071
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Evan Cheng authored
llvm-svn: 135068
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Jim Grosbach authored
The immediate is of limited range and the operand type should reflect that. llvm-svn: 135066
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Jim Grosbach authored
llvm-svn: 135063
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Jim Grosbach authored
Catch potential cascading errors on a malformed so_reg operand and bail after the first error. Add some tests for the diagnostics we do want. llvm-svn: 135055
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Jim Grosbach authored
llvm-svn: 135052
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Jim Grosbach authored
Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
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Jim Grosbach authored
llvm-svn: 135047
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Jim Grosbach authored
Update the debug output interface for MCParsedAsmOperand to have a print() method which takes an output stream argument, an << operator which invokes the print method using the given stream, and a dump() method which prints the operand to the dbgs() stream. This makes the interface more consistent with the rest of LLVM, and more convenient to use at the debugger command line. llvm-svn: 135043
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Jay Foad authored
llvm-svn: 135040
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