These operations will have to be synthesized from other instructions.

llvm-svn: 78263

that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256

When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.

llvm-svn: 78244

hardfloat case.

llvm-svn: 78237

llvm-svn: 78232

Patch by Sandeep Patel!

llvm-svn: 78225

llvm-svn: 78219

llvm-svn: 78216

llvm-svn: 78209

llvm-svn: 78207

llvm-svn: 78200

llvm-svn: 78175

llvm-svn: 78146

Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.

This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.

This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.

llvm-svn: 78142

calls were originally put in place because errs() at one time was
not unbuffered, and these print routines are commonly used with errs()
for debugging. However, errs() is now properly unbuffered, so the
flush calls are no longer needed. This significantly reduces the
number of write(2) calls for regular asm printing when there are many
small functions.

llvm-svn: 78137

Get rid of yesterday's code to fix the register usage during isel.
Select the new DAG nodes to machine instructions.  The new pre-alloc pass
to choose adjacent registers for these results is not done, so the
results of this will generally not assemble yet.

llvm-svn: 78136

llvm-svn: 78126

For other VLDn and VSTn operations, we need to list the multiple registers
explicitly anyway, so there's no point in special-casing this one usage.

llvm-svn: 78109

llvm-svn: 78104

llvm-svn: 78101

llvm-svn: 78086

llvm-svn: 78085

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

llvm-svn: 78060

llvm-svn: 78059

llvm-svn: 78057

Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler.

llvm-svn: 78032

llvm-svn: 78031

Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.

llvm-svn: 78030

results to fixed registers.

llvm-svn: 78025

llvm-svn: 78024

replicating the logic manually.

llvm-svn: 78011

textual sections.

llvm-svn: 78007

Add a testcase.

llvm-svn: 77992

llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".

llvm-svn: 77971

llvm-svn: 77949

Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.

llvm-svn: 77939

 - The C, C++, MSIL, and Mips backends still need the module.

llvm-svn: 77927

Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918

TLOF, unifying all the dwarf targets at the same time.

llvm-svn: 77889