llvm-svn: 126719

llvm-svn: 126689

llvm-svn: 126687

llvm-svn: 126682

[AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit
      and 256-bit forms.  Because the number of elements in a vector
      does not determine the vector type (4 elements could be v4f32 or
      v4f64), pass the full type of the vector to decode routines.

llvm-svn: 126664

needed two predicate operands before the imm operand.

llvm-svn: 126662

llvm-svn: 126661

patch to the front-end.  Radar 7662569.

llvm-svn: 126655

The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.

llvm-svn: 126651

- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636

llvm-svn: 126578

Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs.

It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568

Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic.

1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557

llvm-svn: 126518

llvm-svn: 126488

llvm-svn: 126477

llvm-svn: 126467

D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312

llvm-svn: 126457

llvm-svn: 126441

Patch by Nathan Jeffords!

llvm-svn: 126425

llvm-svn: 126384

operands starts at index 2, not 1.
rdar://9045024
PR9305

llvm-svn: 126359

llvm-svn: 126322

events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320

llvm-svn: 126315

llvm-svn: 126314

llvm-svn: 126313

llvm-svn: 126298

The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702

llvm-svn: 126295

[AVX] General VUNPCKL codegen support.

llvm-svn: 126264

llvm-svn: 126244

llvm-svn: 126238

llvm-svn: 126226

llvm-svn: 126192

llvm-svn: 126191

up by the dynamic linker, but it's better to use the correct instruction
to begin with.

Fixes rdar://9011034

llvm-svn: 126176

From Dimitry Andric.

llvm-svn: 126168

Patch by Jai Menon.

llvm-svn: 126165

Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770

llvm-svn: 126159

In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)

llvm-svn: 126155