[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl.

llvm-svn: 198909

branch to the next instruction.  This can not be encoded but can be
turned into a NOP.

rdar://15062072

llvm-svn: 198904

llvm-svn: 198893

llvm-svn: 198889

The zext handling added in r197802 wasn't right for RNSBG.  This patch
restricts it to ROSBG, RXSBG and RISBG.  (The tests for RISBG were added
in r197802 since RISBG was the motivating example.)

llvm-svn: 198862

operand into the Value interface just like the core print method is.
That gives a more conistent organization to the IR printing interfaces
-- they are all attached to the IR objects themselves. Also, update all
the users.

This removes the 'Writer.h' header which contained only a single function
declaration.

llvm-svn: 198836

llvm-svn: 198794

llvm-svn: 198791

It's not a real instruction any more and doesn't need encoding information.

llvm-svn: 198778

llvm-svn: 198763

Mark them as requiring 16-bit mode for now, since we don't yet have
relaxation support for FK_Data_2.

llvm-svn: 198762

They do *different* things to %esp, so they are not equivalent.

Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8.

llvm-svn: 198761

We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit
mode, for example, because it might be used for an unofficial form of
the in/out instructions. We actually want to do a better job of validation
*later*. Perhaps *instead* of doing it where we are at the moment.

But for now, doing what validation we *can* do in the place that the code
already has its validation, is an improvement.

llvm-svn: 198760

It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759

Where "where possible" means that it's an immediate value and it's below
0x10000. In fact GAS will either truncate or error with larger values,
and will insist on using the addr32 prefix to get 32-bit addressing. So
perhaps we should do that, in a later patch.

llvm-svn: 198758

JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that
appropriately conditional. And JECXZ needs the prefix instead.

llvm-svn: 198757

I couldn't see how to do this sanely without splitting RETQ from RETL.

Eric says: "sad about the inability to roundtrip them now, but...".
I have no idea what that means, but perhaps it wants preserving in the
commit comment.

llvm-svn: 198756

llvm-svn: 198755

llvm-svn: 198754

llvm-svn: 198753

This fixes the bulk of 16-bit output, and the corresponding test case
x86-16.s now looks mostly like the x86-32.s test case that it was
originally based on. A few irrelevant instructions have been dropped,
and there are still some corner cases to be fixed in subsequent patches.

llvm-svn: 198752

llvm-svn: 198745

Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs.

This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff".  At present, this is only enabled for modern x86 OSX ports.

test changes by David Fang.

llvm-svn: 198744

when lower build_vector if result value type mismatch with operand
value type.

llvm-svn: 198743

llvm-svn: 198740

llvm-svn: 198739

llvm-svn: 198738

Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

llvm-svn: 198735

llvm-svn: 198720

This makes it available to tools that don't link with target (like llvm-ar).

llvm-svn: 198708

With the gnu objc runtime private strings are used. Since we only need to
produce a unique label, the fix is to just drop the asserts.

llvm-svn: 198701

This commit adds the pre-UAL aliases of fconsts and fconstd for
vmov.f32 and vmov.f64. They use an InstAlias rather than a
MnemonicAlias to properly support the predicate operand.

We need to support encoded 8-bit constants in order to implement the
pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this
commit also fixes parsing of encoded floating point constants used
in vmov.f32/vmov.f64 instructions. Now we can support assembly code
like this:

  fconsts s0, #0x70

which is equivalent to vmov.f32 s0, #1.0.

Most of the code was already in place to support this feature.
Previously the code was trying to accept encoded 8-bit float
constants for the vmov.f32/vmov.f64 instructions.  It looks like the
support for parsing encoded floats was lost in a refactoring in
commit r148556 and we did not have any tests in place to catch it.

The change in this commit is to keep the parsed value as a 32-bit
float instead of a 64-bit double because that is what the isFPImm()
function expects to find. There is no loss of precision by using a
32-bit float here because we are still limited to an 8-bit encoded
value in the end.

Additionally, we explicitly reject encoded 8-bit floats for
vmovf.32/64. This is the same as the current behavior, but we now do
it explicitly rather than accidently.

llvm-svn: 198697

llvm-svn: 198696

are part of the core IR library in order to support dumping and other
basic functionality.

Rename the 'Assembly' include directory to 'AsmParser' to match the
library name and the only functionality left their -- printing has been
in the core IR library for quite some time.

Update all of the #includes to match.

All of this started because I wanted to have the layering in good shape
before I started adding support for printing LLVM IR using the new pass
infrastructure, and commandline support for the new pass infrastructure.

llvm-svn: 198688

subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685

[AArch64]Add support to spill/fill D tuples such as DPair/DTriple/DQuad. There is no test cases for D tuple as the original test cases are too large. As the spill/fill of the D tuple is similar to the Q tuple, the correctness can be guaranteed.

llvm-svn: 198684

[AArch64]Add support to copy D tuples such as DPair/DTriple/DQuad and Q tuples such as QPair/QTriple/QQuad. There is no test case for D tuple as the original test cases are too large. As the copy of the D tuple is similar to the Q tuple, the correctness can be guaranteed.

llvm-svn: 198682

Also, correct the offsets for FixupsKindInfo.

llvm-svn: 198681

llvm-svn: 198675

Switch the context to be SmallVectors.  This allows for saving additional
context when providing previous emission sites.

llvm-svn: 198665