- Jan 10, 2014
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Venkatraman Govindaraju authored
[Sparc] Add support for parsing jmpl instruction and make indirect call and jmp instructions as aliases to jmpl. llvm-svn: 198909
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David Blaikie authored
This reverts commit r198865 which reverts r198851. ASan identified a use-of-uninitialized of the DwarfTypeUnit::Ty variable in skeleton type units. llvm-svn: 198908
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Kevin Enderby authored
branch to the next instruction. This can not be encoded but can be turned into a NOP. rdar://15062072 llvm-svn: 198904
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- Jan 09, 2014
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NAKAMURA Takumi authored
It caused undefined behavior. DwarfTypeUnit::Ty might not be initialized properly, I guess. llvm-svn: 198865
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Stepan Dyatkovskiy authored
Detailed description is here: http://llvm.org/bugs/show_bug.cgi?id=18000#c16 For participation in bugfix process special thanks to David Wiberg. llvm-svn: 198863
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Richard Sandiford authored
The zext handling added in r197802 wasn't right for RNSBG. This patch restricts it to ROSBG, RXSBG and RISBG. (The tests for RISBG were added in r197802 since RISBG was the motivating example.) llvm-svn: 198862
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Richard Sandiford authored
At the moment we expect rotates to have the form: (or (shl X, Y), (shr X, Z)) where Y == bitsize(X) - Z or Z == bitsize(X) - Y. This form means that the (or ...) is undefined for Y == 0 or Z == 0. This undefinedness can be avoided by using Y == (C * bitsize(X) - Z) & (bitsize(X) - 1) or Z == (C * bitsize(X) - Y) & (bitsize(X) - 1) for any integer C (including 0, the most natural choice). llvm-svn: 198861
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Richard Sandiford authored
InstCombine converts (sub 32, (add X, C)) into (sub 32-C, X), so a rotate left of a 32-bit Y by X+C could appear as either: (or (shl Y, (add X, C)), (shr Y, (sub 32, (add X, C)))) without InstCombine or: (or (shl Y, (add X, C)), (shr Y, (sub 32-C, X))) with it. We already matched the first form. This patch handles the second too. llvm-svn: 198860
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Lang Hames authored
root path to which object files managed by the LLIObjectCache instance should be written. This option defaults to "", in which case objects are cached in the same directory as the bitcode they are derived from. The load-object-a.ll test has been rewritten to use this option to support testing in environments where the test directory is not writable. llvm-svn: 198852
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David Blaikie authored
llvm-svn: 198851
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Saleem Abdulrasool authored
Rename bytecode to opcodes to make it more clear. Change an impossible case to llvm_unreachable instead. Avoid allocation of a buffer by modifying the PrintOpcodes iteration. llvm-svn: 198848
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David Blaikie authored
llvm-svn: 198846
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Andrew Trick authored
In the stackmap format we advertise the constant field as signed. However, we were determining whether to promote to a 64-bit constant pool based on an unsigned comparison. This fix allows -1 to be encoded as a small constant. llvm-svn: 198816
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David Blaikie authored
This makes it easier to write a test that's mostly shared between fission and non-fission (using FileCheck's multiple prefix support). llvm-svn: 198806
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- Jan 08, 2014
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Hal Finkel authored
MIsNeedChainEdge, which is used by -enable-aa-sched-mi (AA in misched), had an llvm_unreachable when -enable-aa-sched-mi is enabled and we reach an instruction with multiple MMOs. Instead, return a conservative answer. This allows testing -enable-aa-sched-mi on x86. Also, this moves the check above the isUnsafeMemoryObject checks. isUnsafeMemoryObject is currently correct only for instructions with one MMO (as noted in the comment in isUnsafeMemoryObject): // We purposefully do no check for hasOneMemOperand() here // in hope to trigger an assert downstream in order to // finish implementation. The problem with this is that, had the candidate edge passed the "!MIa->mayStore() && !MIb->mayStore()" check, the hoped-for assert would never happen (which could, in theory, lead to incorrect behavior if one of these secondary MMOs was volatile, for example). llvm-svn: 198795
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Ana Pazos authored
llvm-svn: 198791
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Roman Divacky authored
resolution works. llvm-svn: 198780
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Andrea Di Biagio authored
to the following two rules: 1) fold (vselect (build_vector AllOnes), A, B) -> A 2) fold (vselect (build_vector AllZeros), A, B) -> B llvm-svn: 198777
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Lang Hames authored
llvm-svn: 198772
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David Woodhouse authored
llvm-svn: 198763
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David Woodhouse authored
They do *different* things to %esp, so they are not equivalent. Rename PUSHi8 to PUSH32i8 and add the missing PUSH16i8. llvm-svn: 198761
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David Woodhouse authored
We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
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David Woodhouse authored
It seems there is no separate instruction class for having AdSize *and* OpSize bits set, which is required in order to disambiguate between all these instructions. So add that to the disassembler. Hm, perhaps we do need an AdSize16 bit after all? llvm-svn: 198759
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David Woodhouse authored
Where "where possible" means that it's an immediate value and it's below 0x10000. In fact GAS will either truncate or error with larger values, and will insist on using the addr32 prefix to get 32-bit addressing. So perhaps we should do that, in a later patch. llvm-svn: 198758
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David Woodhouse authored
JCXZ should have the 0x67 prefix only if we're in 32-bit mode, so make that appropriately conditional. And JECXZ needs the prefix instead. llvm-svn: 198757
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David Woodhouse authored
I couldn't see how to do this sanely without splitting RETQ from RETL. Eric says: "sad about the inability to roundtrip them now, but...". I have no idea what that means, but perhaps it wants preserving in the commit comment. llvm-svn: 198756
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David Woodhouse authored
llvm-svn: 198755
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David Woodhouse authored
llvm-svn: 198754
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David Woodhouse authored
llvm-svn: 198753
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David Woodhouse authored
This fixes the bulk of 16-bit output, and the corresponding test case x86-16.s now looks mostly like the x86-32.s test case that it was originally based on. A few irrelevant instructions have been dropped, and there are still some corner cases to be fixed in subsequent patches. llvm-svn: 198752
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Elena Demikhovsky authored
llvm-svn: 198745
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Iain Sandoe authored
Modern versions of OSX/Darwin's ld (ld64 > 97.17) have an optimisation present that allows the back end to omit relocations (and replace them with an absolute difference) for FDE some text section refs. This patch allows a backend to opt-in to this behaviour by setting "DwarfFDESymbolsUseAbsDiff". At present, this is only enabled for modern x86 OSX ports. test changes by David Fang. llvm-svn: 198744
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Kevin Qin authored
when lower build_vector if result value type mismatch with operand value type. llvm-svn: 198743
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Venkatraman Govindaraju authored
llvm-svn: 198740
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Venkatraman Govindaraju authored
llvm-svn: 198738
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Saleem Abdulrasool authored
Appease the buildbots for targets which do not build the ARM support by moving the ARM specific test into a subdirectory and use the lit configuration to disable them appropriately. Thanks to chapuni and thakis for explaining how to do this! llvm-svn: 198736
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Saleem Abdulrasool authored
Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
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Saleem Abdulrasool authored
This adds some preliminary support for decoding ARM EHABI unwinding information. The major functionality that remains from complete support is bytecode translation. Each Unwind Index Table is printed out as a separate entity along with its section index, name, offset, and entries. Each entry lists the function address, and if possible, the name, of the function to which it corresponds. The encoding model, personality routine or index, and byte code is also listed. llvm-svn: 198734
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Hao Liu authored
Fix a bug about generating undef operand when optimising shuffle vector and insert element in instruction combine. llvm-svn: 198730
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- Jan 07, 2014
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Roman Divacky authored
take type from the new symbol but merge them so that the type is never "downgraded". This is probably quite rare, except for IFUNC symbols which we used to misassemble, losing the IFUNC type. Fixes #18372. llvm-svn: 198706
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