Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.

The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518

llvm-svn: 74515

llvm-svn: 74510

llvm-svn: 74509

llvm-svn: 74508

llvm-svn: 74507

llvm-svn: 74500

llvm-svn: 74499

This will allow it to be used in unittests that use gtest's
EXPECT_EQ.

llvm-svn: 74494

llvm-svn: 74492

llvm-svn: 74491

 - Don't print "Parsing" in front of every message.

 - Take additional "type" argument which is prepended to the message (with ": ")
   if given.

 - Update clients to print errors (warnings) as:
<filename>:<line number>: error(warning): ...

llvm-svn: 74489

Add LLVMContext, which will eventually be used as a container for privatizing a lot of (currently) global state, including the
constant and type uniquing tables.  For now, just make it a wrapper around the existing APIs.

llvm-svn: 74488

llvm-svn: 74483

llvm-svn: 74482

llvm-svn: 74478

llvm-svn: 74477

llvm-svn: 74473

Add a 256-bit register class and YMM registers.

llvm-svn: 74469

llvm-svn: 74468

Constant. This lets ConstantInts be handled as SCEVConstant instead
of SCEVUnknown, as getUnknown no longer has special-case code for
ConstantInt and friends. This usually doesn't affect the final
output, since the constants end up getting folded later, but it
does make intermediate expressions more obvious in many cases.

llvm-svn: 74459

module support to build).

llvm-svn: 74456

llvm-svn: 74455

llvm-svn: 74452

Update dwarf writer to only emit one DW_TAG_compile_unit per .o file. 

llvm-svn: 74449

an individual exhaustive evaluation reflects only the exit value
implied by an individual exit, which may differ from the actual
exit value of the loop if there are other exits. This fixes PR4477.

llvm-svn: 74447

Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.

llvm-svn: 74446

Not doing so causes some unittests to fail, because CurSection is uninitialized.

llvm-svn: 74442

llvm-svn: 74440

llvm-svn: 74439

Also don't call finalizers for LoopPass if initialization was not called.
Add a unittest that tests that these methods are called, in the proper
order, and the correct number of times.

llvm-svn: 74438

(otherwise harmless) uninitialized value warnings that
Duncan found with gcc-4.4.

llvm-svn: 74437

fence-atomic-fence down to just the atomic op.  This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.

llvm-svn: 74435

Add processor descriptions for Istanbul and Shanghai.

llvm-svn: 74429

Fix a subtarget feature bug.

llvm-svn: 74428

Add more vector ValueTypes for AVX and other extended vector instruction
sets.

llvm-svn: 74427

Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.

llvm-svn: 74423

llvm-svn: 74422

to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.

llvm-svn: 74421

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420