llvm-svn: 137712

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

llvm-svn: 137707

llvm-svn: 137706

llvm-svn: 137702

to be wrong (or at least somewhat suspect).  Leave a FIXME for Bill.

llvm-svn: 137694

llvm-svn: 137693

This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?

llvm-svn: 137691

llvm-svn: 137690

llvm-svn: 137689

Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.

llvm-svn: 137686

also add the AVX versions of the 128-bit patterns

llvm-svn: 137685

predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684

llvm-svn: 137683

llvm-svn: 137679

Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675

llvm-svn: 137673

llvm-svn: 137672

llvm-svn: 137668

llvm-svn: 137667

llvm-svn: 137664

llvm-svn: 137663

llvm-svn: 137662

when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661

There is no need to maintain a set to keep track of variables that use location expressions. In such cases, AT_location attribute's value will be a label.

llvm-svn: 137659

llvm-svn: 137658

llvm-svn: 137656

write to memory.) Marking it as such makes some checks for immobility go away.

llvm-svn: 137655

llvm-svn: 137654

llvm-svn: 137652

llvm-svn: 137650

llvm-svn: 137648

Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode.  Update tests to reflect this fact.
Patch by James Molloy.

llvm-svn: 137647

llvm-svn: 137643

llvm-svn: 137642

llvm-svn: 137641

When a variable is inlined multiple places, abstract variable keeps name, location, type etc.. info and all other concreate instances of the variable directly refers to abstract variable.

llvm-svn: 137637

llvm-svn: 137636

Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.

llvm-svn: 137635

llvm-svn: 137632