the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471

the new ParseInstruction method just parses and returns a list of
target operands.  A new MatchInstruction interface is used to
turn the operand list into an MCInst.

This requires new/deleting all the operands, but it also gives 
targets the ability to use polymorphic operands if they want to. 

llvm-svn: 93469

llvm-svn: 93467

Pass in SMLoc of instr opcode into ParseInstruction.
Make AsmToken be a class, not a struct.

llvm-svn: 93457

llvm-svn: 93455

llvm-svn: 93454

This is consistent with llvm-gcc's arm/constraints.md.

Certain instructions (e.g. CBZ, CBNZ) require a low register, even in Thumb2
mode.

llvm-svn: 93436

An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

llvm-svn: 93393

llvm-svn: 93373

llvm-svn: 93372

obsolete Mangler interfaces.

llvm-svn: 93356

llvm-svn: 93351

llvm-svn: 93349

llvm-svn: 93342

llvm-svn: 93341

SelectSectionForGlobal, unbreaking weak globals with no-name.

llvm-svn: 93336

llvm-svn: 93334

llvm-svn: 93333

llvm-svn: 93332

llvm-svn: 93310

llvm-svn: 93309

on linux (even though they are pointless, they shouldn't ICE).

llvm-svn: 93308

llvm-svn: 93307

llvm-svn: 93305

instead of returning it in an std::string.  Based on this change:

1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
   making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
   prefixes, not use temporary std::strings, and to avoid other crimes.

llvm-svn: 93298

It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280

Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.

llvm-svn: 93278

llvm-svn: 93245

on x86-64 linux with messages like this:
Error: Incorrect register `%r14' used with `l' suffix

llvm-svn: 93242

llvm-svn: 93235

to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.

llvm-svn: 93234

llvm-svn: 93229

instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.

llvm-svn: 93210

Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.

llvm-svn: 93204

Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.

llvm-svn: 93191

llvm-svn: 93185

llvm-svn: 93182

- getToken is modeled after StringRef::split but it can split on multiple
  separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
  same behaviour as getToken.

llvm-svn: 93161

has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160

new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158