Commits · 0f7efaf956d4543829dc5d56e2a0c6eddb48f188 · Roger Ferrer / llvm-epi-0.8

Oct 04, 2011
- Un-XFAIL file. Comment out individual failing instructions. · 4879f70a
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141117
```
  4879f70a
- Tidy up formatting. · f3e1fc3f
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141115
```
  f3e1fc3f
- Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup. · 8a829e8e
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141114
```
  8a829e8e
- Un-XFAIL file. Fix incorrect CHECK line. General format cleanup. · 8bc8bfdc
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141113
```
  8bc8bfdc
- Tidy up formatting. · 610aa62e
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141111
```
  610aa62e
- Un-XFAIL file. Fix incorrect CHECK line. · 388c0f61
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141110
```
  388c0f61
- Un-XFAIL the file. Disable only the individual tests that aren't working yet. · 2644375a
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141108
```
  2644375a
- Un-XFAIL the file. Disable only the individual tests that aren't working yet. · 83e84faa
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141099
```
  83e84faa
- Tidy up. Formatting. · 2d9eb707
  Jim Grosbach authored Oct 04, 2011
```
llvm-svn: 141096
```
  2d9eb707
- Add support in the disassembler for ignoring the L-bit on certain VEX... · f18c8963
  Craig Topper authored Oct 04, 2011
```
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065
```
  f18c8963
- Tidy up. These tests are covered in the .s file tests now. · b85400aa
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141047
```
  b85400aa
- ARM assembly parsing and encoding for VMOV immediate. · e7fbce7a
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141046
```
  e7fbce7a
- ARM parsing/encoding for VCMP/VCMPE. · 46b66460
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141038
```
  46b66460
Oct 03, 2011
- ARM assembly parsing and encoding for VMRS/FMSTAT. · 4ab23b52
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141025
```
  4ab23b52
- Update test for 141010. · c3fc62b4
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141022
```
  c3fc62b4
- Tidy up a bit. Formatting. · b817655b
  Jim Grosbach authored Oct 03, 2011
```
llvm-svn: 141010
```
  b817655b
- Add support for MOVBE and RDRAND instructions for the assembler and... · 786bdb9e
  Craig Topper authored Oct 03, 2011
```
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.

llvm-svn: 141007
```
  786bdb9e
- Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to... · 0d0be47d
  Craig Topper authored Oct 03, 2011
```
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.

llvm-svn: 140997
```
  0d0be47d
- Test updates that were supposed to go with r140993. · 285bc340
  Craig Topper authored Oct 03, 2011
```
llvm-svn: 140994
```
  285bc340
Oct 02, 2011

Fix some Intel syntax disassembly issues with instructions that implicitly use... · 7aea69d9

Craig Topper authored Oct 02, 2011

Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.

llvm-svn: 140974

7aea69d9

Special case disassembler handling of REX.B prefix on NOP instruction to... · 21c33657

Craig Topper authored Oct 02, 2011

Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.

llvm-svn: 140971

21c33657

Oct 01, 2011

Fix disassembling of INVEPT and INVVPID to take operands · d07a59f2
Craig Topper authored Oct 01, 2011
```
llvm-svn: 140955
```
d07a59f2

Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2... · 88cb33e0

Craig Topper authored Oct 01, 2011

Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

88cb33e0

Sep 28, 2011

Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. · 21efa7d6

James Molloy authored Sep 28, 2011

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696

21efa7d6

ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. · c63af1b7
Jim Grosbach authored Sep 27, 2011
```
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
```
c63af1b7

Sep 27, 2011
- Fix an incorrect decoder test. · 287d6ef0
  Owen Anderson authored Sep 26, 2011
```
llvm-svn: 140579
```
  287d6ef0
- Remove incorrect testcases. · d20cd25c
  Owen Anderson authored Sep 26, 2011
```
llvm-svn: 140572
```
  d20cd25c
Sep 26, 2011
- Fix VEX decoding in i386 mode. Fixes PR11008. · 45faba98
  Craig Topper authored Sep 26, 2011
```
llvm-svn: 140515
```
  45faba98
Sep 24, 2011
- Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. · 4916840e
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140426
```
  4916840e
- Fix incorrect disassembly test. · b7577220
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140423
```
  b7577220
Sep 23, 2011
- Post-index loads/stores in still need to print the post-indexed immediate,... · 737beaf8
  Owen Anderson authored Sep 23, 2011
```
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

llvm-svn: 140420
```
  737beaf8
- Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. · 987a8789
  Owen Anderson authored Sep 23, 2011
```
llvm-svn: 140415
```
  987a8789
- Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. · 526adabe
  Craig Topper authored Sep 23, 2011
```
llvm-svn: 140370
```
  526adabe
Sep 22, 2011
- Fix register printing in disassembling of push/pop of segment registers and... · 6d1872b7
  Craig Topper authored Sep 22, 2011
```
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960

llvm-svn: 140299
```
  6d1872b7
- Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix... · fbe52c01
  Owen Anderson authored Sep 21, 2011
```
Turns out that Thumb2 ADR doesn't need special printing like LDR does.  Fix other test failures I caused.

llvm-svn: 140284
```
  fbe52c01
- Print out immediate offset versions of PC-relative load/store instructions as... · f52c68f0
  Owen Anderson authored Sep 21, 2011
```
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283
```
  f52c68f0
Sep 20, 2011
- The wrong relocation was being emitted for several SSSE3 instructions. · 33e91a6c
  Bruno Cardoso Lopes authored Sep 20, 2011
```
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

llvm-svn: 140184
```
  33e91a6c
- Port over more Thumb2 encoding tests to decoding tests. · 2b35d7cf
  Owen Anderson authored Sep 20, 2011
```
llvm-svn: 140152
```
  2b35d7cf
- Nuke obsolete test file. · a316da14
  Jim Grosbach authored Sep 20, 2011
```
llvm-svn: 140127
```
  a316da14
- Thumb2 assembly parsing and encoding for WFE/WFI/YIELD. · c70d9dfa
  Jim Grosbach authored Sep 20, 2011
```
llvm-svn: 140126
```
  c70d9dfa