even some the old isel didn't.  There are several parts of
this that make me feel dirty, but it's no worse than the
old isel.  I'll clean up the parts I can do without ripping
out the old one next.

llvm-svn: 97415

llvm-svn: 97414

llvm-svn: 97413

llvm-svn: 97412

llvm-svn: 97411

llvm-svn: 97409

llvm-svn: 97408

APInt.  Be certain to set the integer bit in an x87 extended-precision
significand so that we don't accidentally make a pseudo-NaN.

llvm-svn: 97382

It gets its own implementation totally divorced from the (presumably
performance-sensitive) routines which parse into a uint64_t.

Add APInt::operator|=(uint64_t), which is situationally much better than
using a full APInt.

llvm-svn: 97381

llvm-svn: 97380

llvm-svn: 97379

llvm-svn: 97378

llvm-svn: 97377

llvm-svn: 97376

llvm-svn: 97375

llvm-svn: 97374

llvm-svn: 97372

llvm-svn: 97371

llvm-svn: 97370

llvm-svn: 97369

llvm-svn: 97368

llvm-svn: 97367

llvm-svn: 97366

payloads.  APFloat's internal folding routines always make QNaNs now,
instead of sometimes making QNaNs and sometimes SNaNs depending on the
type.

llvm-svn: 97364

it will populate.

llvm-svn: 97363

because I have to go on another detour first.

llvm-svn: 97362

llvm-svn: 97360

after LSR, so that clients can opt in.

llvm-svn: 97357

node is always guaranteed to have a particular type 
instead of hacking in ISD::STORE explicitly.  This allows
us to use implied types for a broad range of nodes, even
target specific ones.

llvm-svn: 97355

Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354

defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

llvm-svn: 97349

llvm-svn: 97348

the opcode name.  This gives the optimizer more semantic info.

llvm-svn: 97346

but codegen'd differently.  This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something.  However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.

llvm-svn: 97345

dissatisfying hack.  TODO: Improve it. :)

llvm-svn: 97317

llvm-svn: 97316

llvm-svn: 97315

with getType() == MVT::i32 etc.  Teach it that two different
integer constants are contradictory.  This cuts 1K off the X86
table, down to 98k

llvm-svn: 97314

llvm-svn: 97313