and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

llvm-svn: 108567

Thumb2ITBlockPass.

llvm-svn: 108564

thus is a much more meaningful name.

llvm-svn: 108563

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

llvm-svn: 108396

instructions use different values (e.g., 2-byte or 4-byte alignment).
Also fix ARMInstPrinter to print these alignments as bits instead of bytes.

llvm-svn: 108386

llvm-svn: 108366

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Patch by Brian Lucas. PR7636.

llvm-svn: 108332

llvm-svn: 108328

llvm-svn: 108324

of the value of the immediate.

llvm-svn: 108323

Radar 7373643.

llvm-svn: 108303

NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

llvm-svn: 108256

avoid replicated code.

llvm-svn: 108227

instructions already have implicit defs of LR.  The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.

llvm-svn: 108186

llvm-svn: 108130

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099

llvm-svn: 108094

llvm-svn: 108078

correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072

llvm-svn: 108043

llvm-svn: 108012

rdar://8131327

llvm-svn: 108008

consistency with other instructions that have lists of register operands.

llvm-svn: 107944

llvm-svn: 107904

This pass can go away entirely soon.

llvm-svn: 107892

words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

llvm-svn: 107890

llvm-svn: 107882

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879

llvm-svn: 107856

Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

llvm-svn: 107852

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

llvm-svn: 107831

address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830

llvm-svn: 107811

code can do calling-convention queries. This obviates OutputArgReg.

llvm-svn: 107786