instructions to the Intel instruction tables.

llvm-svn: 82084

instruction tables.

llvm-svn: 82083

to the Intel instruction tables.

llvm-svn: 82081

llvm-svn: 82074

llvm-svn: 82054

and use MachineModuleInfoMachO instead.

llvm-svn: 82022

llvm-svn: 82020

stuff common across all macho targets.

llvm-svn: 82018

llvm-svn: 82011

the global variable list only happen for COFF targets.

llvm-svn: 82010

we have MCInstPrinter.

llvm-svn: 82006

llvm-svn: 81999

trying to create RMW opportunities in the x86 backend.  This can cause a 
cycle to appear in the graph, since the other uses may eventually feed into
the TokenFactor we are sinking the load below.

llvm-svn: 81996

frame, to the Intel instruction tables.

llvm-svn: 81995

the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.

llvm-svn: 81994

covered by other definitions.

llvm-svn: 81992

Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.

To replace their functionality, add a new 
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.

The default implementation just returns the symbol.  The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub.  The bizarro x86-64 darwin specialization
handles the weird "foo@GOTPCREL+4" hack.

DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another 
horrible hack from DwarfException.cpp:

-    if (strcmp(MAI->getPersonalitySuffix(), "+4@GOTPCREL"))
-      O << "-" << MAI->getPCSymbol();

llvm-svn: 81991

All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.

llvm-svn: 81979

llvm-svn: 81969

llvm-svn: 81966

and use PersonalityPrefix/Suffix to achieve the same effect (like
the x86 backend).

This changes the code generated for ppc static mode, but guess what,
we were generating this before:

	.byte	0x9B                                        ; Personality (indirect pcrel sdata4)
	.long	___gxx_personality_v0-.                     ; Personality

which is not correct! (it is not an 'indirect' reference).
 

llvm-svn: 81965

Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)

llvm-svn: 81959

code in other segments) to the Intel instruction
tables.

llvm-svn: 81953

llvm-svn: 81923

Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914

to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895

interrupt instruction, which shouldn't arise any other way).  0xcd is
also used by JITMemoryManager to initialize the buffer to garbage,
which means it could appear following a noreturn call even when
that is not a stub, confusing X86CompilationCallback2.  PR 4929.

llvm-svn: 81888

values to machineinstrs.

llvm-svn: 81886

llvm-svn: 81881

VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR.  The asm printer,
however, silently drops the offset, producing incorrect code.  Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.

llvm-svn: 81879

llvm-svn: 81878

and PIC codegen.  Patch by Venkatraman Govindaraju!

llvm-svn: 81877

llvm-svn: 81827

has multiple uses, as one of the other uses may be on a path
to a different node above the callseq_start, because that
leads to a cyclic graph. This problem is exposed when
-combiner-global-alias-analysis is used. This fixes PR4880.

llvm-svn: 81821

versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.

llvm-svn: 81818

parses the .word directive as 4 bytes and ARMAsmParser::ParseInstruction will
give an error is called.  Broke out the test of the .word directive into two
different test cases, one for x86 and one for arm.

llvm-svn: 81817

its result if the condition is false.

llvm-svn: 81814

llvm-svn: 81773

llvm-svn: 81770

llvm-svn: 81755