- Aug 17, 2012
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Akira Hatanaka authored
No new tests are added. All tests in ExecutionEngine/MCJIT that have been failing pass after this patch is applied (when "make check" is done on a mips board). Patch by Petar Jovanovic. llvm-svn: 162135
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Jakob Stoklund Olesen authored
PEI can't handle the pseudo-instructions. This can be removed when the pseudo-instructions are replaced by normal predicated instructions. Fixes PR13628. llvm-svn: 162130
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Akira Hatanaka authored
Patch by Vladimir Medic. llvm-svn: 162124
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Bill Wendling authored
make it more consistent with its intended semantics. The `linker_private_weak_def_auto' linkage type was meant to automatically hide globals which never had their addresses taken. It has nothing to do with the `linker_private' linkage type, which outputs the symbols with a `l' (ell) prefix among other things. The intended semantic is more like the `linkonce_odr' linkage type. Change the name of the linkage type to `linkonce_odr_auto_hide'. And therefore changing the semantics so that it produces the correct output for the linker. Note: The old linkage name `linker_private_weak_def_auto' will still parse but is not a synonym for `linkonce_odr_auto_hide'. This should be removed in 4.0. <rdar://problem/11754934> llvm-svn: 162114
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Jakob Stoklund Olesen authored
llvm-svn: 162107
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Tim Northover authored
llvm-svn: 162094
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Craig Topper authored
llvm-svn: 162089
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Craig Topper authored
Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler. llvm-svn: 162088
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Craig Topper authored
llvm-svn: 162086
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Jakob Stoklund Olesen authored
It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
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Jakob Stoklund Olesen authored
Use the target independent select analysis hooks. llvm-svn: 162060
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- Aug 16, 2012
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Roman Divacky authored
llvm-svn: 162039
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Roman Divacky authored
llvm-svn: 162037
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Roman Divacky authored
llvm-svn: 162032
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Jush Lu authored
Without fastcc support, the caller just falls through to CallingConv::C for fastcc, but callee still uses fastcc, this inconsistency of calling convention is a problem, and fastcc support can fix it. llvm-svn: 162013
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Anitha Boyapati authored
llvm-svn: 162012
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Anitha Boyapati authored
llvm-svn: 162010
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Akira Hatanaka authored
floats. llvm-svn: 162008
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Jakob Stoklund Olesen authored
The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
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- Aug 15, 2012
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Evan Cheng authored
Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029 llvm-svn: 161962
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Jakob Stoklund Olesen authored
When predicating this instruction: Rd = ADD Rn, Rm We need an extra operand to represent the value given to Rd when the predicate is false: Rd = ADDCC Rfalse, Rn, Rm, pred The Rd and Rfalse operands are different registers while in SSA form. Rfalse is tied to Rd to make sure they get the same register during register allocation. Previously, Rd and Rn were tied, but that is not required. Compare to MOVCC: Rd = MOVCC Rfalse, Rtrue, pred llvm-svn: 161955
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Anton Korobeynikov authored
reversed. This leads to wrong codegen for float-to-half conversion intrinsics which are used to support storage-only fp16 type. NEON variants of same instructions are fine. llvm-svn: 161907
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Eric Christopher authored
llvm-svn: 161906
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Michael Liao authored
llvm-svn: 161902
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- Aug 14, 2012
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Michael Liao authored
- FP_EXTEND only support extending from vectors with matching elements. This results in the scalarization of extending to v2f64 from v2f32, which will be legalized to v4f32 not matching with v2f64. - add X86-specific VFPEXT supproting extending from v4f32 to v2f64. - add BUILD_VECTOR lowering helper to recover back the original extending from v4f32 to v2f64. - test case is enhanced to include different vector width. llvm-svn: 161894
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Jim Grosbach authored
Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
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Craig Topper authored
llvm-svn: 161860
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Craig Topper authored
Re-factor intrinsic lowering to combine common parts of similar intrinsics. Reduces compiled code size a little bit. llvm-svn: 161859
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- Aug 13, 2012
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Jakob Stoklund Olesen authored
It never does anything when running 'make check', and it get's in the way of updating live intervals in 2-addr. The hook was originally added to help form IT blocks in Thumb2 code before register allocation, but the pass ordering has changed since then, and we run if-conversion after register allocation now. When the MI scheduler is enabled, there will be no less than two schedulers between 2-addr and Thumb2ITBlockPass, so this hook is unlikely to help anything. llvm-svn: 161794
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Manman Ren authored
This change is to be enabled in clang. rdar://9877866 llvm-svn: 161789
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Arnold Schwaighofer authored
This was causing unnecessary spills/restores of callee saved registers. Fixes PR13572. Patch by Pranav Bhandarkar! llvm-svn: 161778
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Nadav Rotem authored
Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
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Manman Ren authored
OpTbl1 to OpTbl2 since they have 3 operands and the last operand can be changed to a memory operand. PR13576 llvm-svn: 161769
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Eric Christopher authored
Patch by Weiming Zhao. llvm-svn: 161768
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Manman Ren authored
Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6. llvm-svn: 161763
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Tim Northover authored
Previously, we used VLD1.32 in all cases, however there are both 16 and 64-bit accesses being selected, so we need to use an appropriate width load in those cases. llvm-svn: 161748
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Craig Topper authored
Tidy up VSETCC lowering code a bit more by adding an llvm_unreachable and putting an a couple if conditions in a better order. llvm-svn: 161746
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Craig Topper authored
llvm-svn: 161745
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Craig Topper authored
llvm-svn: 161743
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Craig Topper authored
Remove the LowerMMXCONCAT_VECTORS function. It could never execute because there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. llvm-svn: 161742
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